SI5320-H-GL Silicon Laboratories Inc, SI5320-H-GL Datasheet
SI5320-H-GL
Specifications of SI5320-H-GL
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SI5320-H-GL Summary of contents
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... SONET/SDH line/port cards Optical modules Description The Si5320 is a precision clock multiplier designed to exceed the requirements of high-speed communication systems, including OC-192/OC-48 and 10 GbE. This device phase locks to an input clock in the 19, 39, 78, 155, 311, or 622 MHz frequency range and generates a frequency-multiplied clock output that can be configured for operation in the 19, 155, or 622 MHz range. Silicon Laboratories’ ...
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... Si5320 2 Rev. 2.5 ...
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... Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.10. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.11. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.12. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.13. Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3. Pin Descriptions: Si5320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6. 9x9 mm CBGA Card Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Rev ...
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... All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5320 is guaranteed by design to operate at –40° C. All electrical specifications are guaranteed for an ambient temperature of –20 to 85° C. ...
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... C LKIN + C LKIN – peration with Single-Ended C lock Input N ote: W hen using single-ended clock sources, the unused clock input on the Si5320 m ust be ac-coupled to ground. C LKIN + C LKIN – (C LKIN+) – (C LKIN – peration with D ifferential C lock Input N ote: Transm ission line term ination, when required, m ust be provided Figure 1 ...
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... Clock inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input should be ac coupled to ground. 3. Transmission line termination, when required, must be provided externally. 4. Although the Si5320 device can operate with input clock swings as high as 1500 mV maintaining the input clock amplitude below 500 ...
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... CLKOUT Fall Time Output Clock Duty Cycle RSTN/CAL Pulse Width *Note: The Si5320 provides a 1/32, 1/16, 1/8, 1/4, 1/ 16, or 32x clock frequency multiplication function with an option for additional frequency scaling by a factor of 255/238 or 238/255 for FEC rate compatibility. Symbol Test Condition ...
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... INFRQSEL[2:0] = 110 Recovery Time for Clearing an LOS Condition VALTIME = 0 VALTIME = 1 *Note: The Si5320 provides a 1/32, 1/16, 1/8, 1/4, 1/ 16, or 32x clock frequency multiplication function with an option for additional frequency scaling by a factor of 255/238 or 238/255 for FEC rate compatibility. 8 Symbol Test Condition ...
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... For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/μs unit is used here since the maximum phase transient magnitude for the Si5320 (tPT_MTIE) never reaches one nanosecond. Symbol Test Condition ...
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... For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/μs unit is used here since the maximum phase transient magnitude for the Si5320 (tPT_MTIE) never reaches one nanosecond. 10 Symbol ...
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... For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/μs unit is used here since the maximum phase transient magnitude for the Si5320 (tPT_MTIE) never reaches one nanosecond. Symbol Test Condition ...
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... For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/μs unit is used here since the maximum phase transient magnitude for the Si5320 (tPT_MTIE) never reaches one nanosecond. 12 Symbol ...
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... For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/μs unit is used here since the maximum phase transient magnitude for the Si5320 (tPT_MTIE) never reaches one nanosecond. Symbol Test Condition ...
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... Table 6. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient 0 -20 -40 -60 -80 -100 -120 -140 -160 Figure 4. Typical Si5320 Phase Noise (CLKIN = 155.52 MHz, CLKOUT = 622.08 MHz, and 14 Symbol Value V –0.5 to 3.6 DD33 V –0 DIG ±50 T –55 to 150 JCT T –55 to 150 STG ...
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... Input Clock Frequency Select (19, 38, 77, 155, 311, or 622 MHz) FEC Scaling Select (14/15, 15/14) PLL Bandwidth Select Bandwidth Doubling Fixed Delay Mode Control LOS Validation Time Reset/Calibration Control Figure 5. Si5320 Typical Application Circuit (3.3 V Supply) 2200 kΩ 1% CLKIN+ CLKIN- INFRQSEL[2:0] Si5320 ...
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... The multiplication factor is configured by selecting the input and output clock frequency ranges for the device. The Si5320 accepts an input clock in the 19, 38, 77, 155, 311, or 622 MHz frequency range. The input frequency range is selected using the INFRQSEL[2:0] pins. The INFRQSEL[2:0] settings and associated output clock rates are given in Table 8. The Si5320’ ...
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... FEC Frequency Scaling 1/1 255/238 238/255 Reserved 2.2.1. FEC Rate Conversion The Si5320 provides a 1/32x, 1/16x, 1/8x, 1/4x, 1/2x, 1x, 2x, 4x, 8x, 16x, or 32x clock frequency multiplication * DBLBW function with an option for additional frequency scaling by a factor of 255/238 or 238/255 for FEC rate 1 1 compatibility ...
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... Table 4 on page 9. 18 2.5. Hitless Recovery from Digital Hold When the Si5320 device is locked to a valid input clock, a loss of the input clock causes the device to automatically switch to digital hold mode. When the input clock signal returns, the device performs a “ ...
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... LOS condition is declared, the Si5320 goes into digital hold mode, and the LOS output alarm signal is set high. The LOS sampling circuitry runs at a frequency of f ...
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... Si5320 2.9. Bias Generation Circuitry The Si5320 makes use of an external resistor to set internal bias currents. The external resistor allows precise generation of bias currents which significantly reduces power consumption and variation as compared with traditional implementations that use an internal resistor. The bias generation circuitry requires a 10 kΩ ...
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... Design and Layout Guidelines Precision clock circuits are susceptible to board noise and EMI. To take precautions against unacceptable levels of board noise and EMI affecting performance of the Si5320, consider the following: Power the device from 3.3 V since the internal regulator provides at least isolation to the V pins (which power the PLL circuitry) ...
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... Pin Descriptions: Si5320 8 7 RSVD_NC RSVD_NC RSVD_NC RSVD_GND RSVD_GND GND DH_ACTV VDD25 CAL_ACTV VDD25 LOS VDD25 GND GND FRQSEL[1] CLKOUT– Figure 11. Si5320 Pin Configuration (Bottom View RSVD_NC RSVD_NC RSVD_NC FEC[0] RSVD_GND RSVD_NC FXDDELAY RSVD_GND GND GND GND GND VDD25 VDD33 ...
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... GND D CLKIN+ DBLBW VDD33 E CLKIN– GND VDD33 F INFRQSEL[0] GND VDD25 G INFRQSEL[1] GND GND H INFRQSEL[2] REXT RSTN/CAL Figure 12. Si5320 Pin Configuration (Transparent Top View RSVD_NC RSVD_NC RSVD_NC RSVD_NC FXDDELAY RSVD_NC RSVD_GND RSVD_GND GND GND GND GND VDD33 VDD33 VDD25 VDD25 VDD33 ...
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... Pin Name B4 FXDDELAY D1 CLKIN+ E1 CLKIN– *Note: The LVTLL inputs on the Si5320 device have an internal pulldown mechanism that causes these inputs to default to a logic low state if the input is not driven from an external source. 24 Table 11. Si5320 Pin Descriptions I/O Signal Level I* LVTTL Fixed Delay Mode ...
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... F8 LOS D8 DH_ACTV H3 RSTN/CAL *Note: The LVTLL inputs on the Si5320 device have an internal pulldown mechanism that causes these inputs to default to a logic low state if the input is not driven from an external source. Signal Level I* LVTTL Input Frequency Range Select. Pins(INFRQSEL[2:0]) select the frequency range for the input clock, CLKIN ...
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... H5 FRQSEL[0] H8 FRQSEL[1] A3 FEC[0] A2 FEC[1] *Note: The LVTLL inputs on the Si5320 device have an internal pulldown mechanism that causes these inputs to default to a logic low state if the input is not driven from an external source. 26 I/O Signal Level O CML Differential Clock Output. High frequency clock output. The frequency of the CLKOUT output is a multiple of the frequency of the CLKIN input ...
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... E3–E5 D6, D7, E6 DD25 E7, F3–F7 *Note: The LVTLL inputs on the Si5320 device have an internal pulldown mechanism that causes these inputs to default to a logic low state if the input is not driven from an external source. Signal Level I* LVTTL Bandwidth Select. BWSEL[1:0] pins set the bandwidth of the loop filter within the DSPLL to 6400, 3200, 1600, or 800 Hz as indicated below ...
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... GND GND F2, G2–G8 H2 REXT D2 DBLBW *Note: The LVTLL inputs on the Si5320 device have an internal pulldown mechanism that causes these inputs to default to a logic low state if the input is not driven from an external source. 28 I/O Signal Level Supply Ground. Must be connected to system ground. Minimize the ground path impedance for optimal performance of the device ...
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... Ordering Guide Part Number Si5320-G-BC Si5320-H-BL Si5320-H-GL Package Temperature Range 63-Ball CBGA – °C (Prior Revision) RoHS-5 63-Ball PBGA – °C (Current Revision) RoHS-5 63-Ball PBGA – °C (Current Revision) RoHS-6 Rev. 2.5 Si5320 29 ...
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... Si5320 5. Package Outline Figure 13 illustrates the package details for the Si5320. Table 12 lists the values for the dimensions shown in the illustration. Figure 13. 63-Ball Plastic Ball Grid Array (PBGA) Table 12. Package Diagram Dimensions (mm) Symbol Min Nom A 1.24 1.41 A1 0.40 0.50 A2 0.34 0. ...
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... The ratio of stencil aperture to land pad size should be 1:1. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Min Nom X 0.40 0.45 C1 7.00 C2 7.00 E1 1.00 E2 1.00 Rev. 2.5 Si5320 Max 0.50 31 ...
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... Updated Figure 13, “63-Ball Plastic Ball Grid Array (PBGA),” on page 30. Updated Table 12, “Package Diagram Dimensions (mm),” on page 30 Added Figure 4, “Typical Si5320 Phase Noise (CLKIN = 155.52 MHz, CLKOUT = 622.08 MHz, and Loop BW = 800 Hz),” on page 14 Revision 2.1 to Revision 2.2 Updated "2.7. Reset" on page 19. ...
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... N : OTES Rev. 2.5 Si5320 33 ...
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... Si5320 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: Clockinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...