SI5023-BM Silicon Laboratories Inc, SI5023-BM Datasheet
SI5023-BM
Specifications of SI5023-BM
Related parts for SI5023-BM
SI5023-BM Summary of contents
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... The Si5022/23 represents a new standard in low jitter, low power, small size, and integration for high-speed LA/CDRs. It operates from either a 3.3 V (Si5023) or 2.5 V (Si5022) supply over the industrial temperature range (– °C). Functional Block Diagram ...
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... Si5022/Si5023 2 Rev. 1.23 ...
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... Bit Error Rate (BER) Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data Slicing Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 RESET/DSPLL Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Pin Descriptions: Si5022/ Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Si5022/Si5023 Rev. 1.23 Page 3 ...
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... Si5022/Si5023 Detailed Block Diagram LOS BER_LVL Signal LOS_LVL Detect DIN+ Limiting Amp Detector DIN+ Slicing SLICE_LVL Control REFCLK± (optional) Bias REXT Generation 4 BER_ALM BERMON LTR BER Monitor Phase A/D DSP VCO n Lock Detection Rev. 1.23 RATESEL[0:1] DSQLCH DOUT+ Retime DOUT– ...
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... Ambient Temperature 2 Si5022 Supply Voltage 2 Si5023 Supply Voltage Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5022/23 specifications are guaranteed when using the recommended application circuit (including component tolerance) of " ...
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... Si5022/Si5023 DOUT CLK OUT DOUT, CLKOUT Figure 3. DOUT and CLKOUT Rise/Fall Times RESET/Cal LOL DATAIN LOL Cf-D C r-D Figure 2. Clock to Data Timing Figure 4. PLL Acquisition Time Rev. 1.23 80% 20% ...
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... DATAIN LOS Figure 5. LOS Response Time Si5022/Si5023 LOS Threshold Level t LOS Rev. 1.23 7 ...
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... Si5022/Si5023 Table 2. DC Characteristics (V = 2.5 V ±5% for Si5022 or 3.3 V ±5% for Si5023 Parameter 1 Supply Current FEC (2.7 GHz) OC-48 GbE OC-12 OC-3 Power Dissipation FEC (2.7 GHz) OC-48 GbE OC-12 OC-3 Power Dissipation FEC (2.7 GHz) OC-48 GbE OC-12 OC-3 Common Mode Input Voltage (DIN) ...
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... Table 2. DC Characteristics (Continued 2.5 V ±5% for Si5022 or 3.3 V ±5% for Si5023 Parameter Input Voltage High (LVTTL Inputs) Input Low Current (LVTTL Inputs) Input High Current (LVTTL Inputs) Input Impedance (LVTTL Inputs) LOS_LVL, BER_LVL, SLICE_LVL Input Impedance Output Voltage Low (LVTTL Outputs) ...
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... Adjustment voltage (relative to the internally set input common mode voltage) is calculated as follows (SLICE_LVL – 1.50)/50. SLICE 2. Adjustment voltage is calculated as follows: V Table 4. AC Characteristics (PLL Characteristics 2.5 V ±5% for Si5022 or 3.3 V ±5% for Si5023 Parameter Jitter Tolerance (OC-48)* Jitter Tolerance * (OC-12 Mode) ...
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... Table 4. AC Characteristics (PLL Characteristics 2.5 V ±5% for Si5022 or 3.3 V ±5% for Si5023 Parameter Input Reference Clock Frequency Tolerance Frequency Difference at which Receive PLL goes out of Lock (REFCLK compared to the divided down VCO clock) Frequency Difference at which Receive PLL goes into Lock ...
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... Si5022/Si5023 Typical Application Schematic Control Inputs DIN+ High Speed Serial Input DIN– System REFCLK+ Reference Clock REFCLK– (Optional) Loss-of-Signal Level Set Bit Error Rate Level Set 12 BER Alarm LVTTL Loss-of-Signal Indicator Indicator Loss-of-Lock Indicator 2 DOUT+ DOUT– Si5022/23 CLKOUT+ CLKOUT– ...
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... Note: Without an external reference, the acquisition of data is dependent solely on the data itself and typically requires more time to acquire lock than when a refer- ence is applied. Rev. 1.23 Si5022/Si5023 OC-48 SONET/ Gigabit with Ethernet 15/14 ...
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... Si5022/Si5023 Operation With an External Reference The Si5022/23 device’s optional external reference clock centers the DSPLL, minimizes the acquisition time, and maintains a stable output clock (CLKOUT) when lock-to-reference (LTR) is asserted. When the reference clock is present, the Si5022/23 will use the reference clock to center the VCO output frequency so that clock and data can be recovered from the input data stream ...
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... Note: There are no entries in the mask table for the data rate corresponding to OC-24 as that rate is not specified by either GR-253 or G.958. Rev. 1.23 Si5022/Si5023 –10 –6 and 10 , respectively. The ( ) V 1 ...
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... Figure 8. Si5023 OC-48 BERMON Voltage Characteristics Si5023 CDR 13.7 kΩ BERMON 5 kΩ 1% *Note: See Table 9 (Si5022/23 Pin Descriptions) Figure 9. Si5023 BERMON Application Schematic 16 Range of Operation 1.E-04 1.E-06 1.E-05 Bit Error Rate 6.8 µ ...
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... The external resistor allows precise generation of bias currents, which significantly reduces power implementations that use an internal resistor. The bias generation circuitry requires a 10 kΩ (1%) resistor connected between REXT and GND. Rev. 1.23 Si5022/Si5023 rms provides a clock disable pin consumption ...
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... The Si5023 regulates 2.5 V internally down from the external 3.3 V supply. Both devices typically consume 148 mA. The Si5023 may accept control inputs as high as 3 addition to supporting 3.3 V systems, the on-chip linear regulator offers better power supply noise rejection versus the direct 2 ...
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... Ω 50 Ω 0.1 µF Figure 14. Single-Ended Input Termination for REFCLK (ac coupled) Signal source 0.1 µ Ω 0.1 µF Figure 15. Single-Ended Input Termination for DIN (ac coupled) Si5022/Si5023 Si5022/23 2.5 V (±5%) 2.5 kΩ RFCLK + 10 kΩ 2.5 kΩ RFCLK – 10 kΩ GND Si5022/23 2 ...
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... Si5022/Si5023 Differential Output Circuitry The Si5022/23 utilizes a CML architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with ac coupling is shown in Figure 16. In applications in which direct dc coupling is possible, the 0.1 µF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is specified in Table 2 ...
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... Differential Reference Clock (Optional). When present, the reference clock sets the center operating frequency of the DSPLL for clock and data recovery. Tie REFCLK+ to VDD and REFCLK– to GND to operate without an external reference clock. See Table 8 for typical reference clock frequencies. Rev. 1.23 Si5022/Si5023 Description 21 ...
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... Note: This input has a weak internal pulldown. 2 Supply Voltage. 3.3 V Nominally 2.5 V for Si5022 and 3.3 V for Si5023. I See Table 2 Differential Data Input. Clock and data are recovered from the differential signal present on these pins. AC coupling is recom- mended ...
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... Figure 8. This pin may be left unconnected. GND Supply Ground. Nominally 0.0 V. The square GND pad found on the bottom of the 28-lead micro leaded package (see Figure 18) must be connected directly to supply ground. Minimize the ground path inductance for optimal performance. Rev. 1.23 Si5022/Si5023 Description 23 ...
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... Si5022/Si5023 Ordering Guide Part Number Si5022-BM Si5023-BM 24 Package Voltage 28-Lead MLP 2.5 28-Lead MLP 3.3 Rev. 1.23 Temperature – °C – °C ...
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... Package Outline Figure 18 illustrates the package details for the Si5022 and Si5023. Table 10 lists the values for the dimensions shown in the illustration. For a pad layout recommendation please contact Silicon Laboratories® D TOP VIEW Figure 18. 28-Lead Micro Leaded Package (MLP) ...
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... Revision 1.22 to Revision 1.23 ! Updated Table 2 on page 8. Added “Output Common Mode Voltage (Si5023) " (DOUT)” with updated values. Added “Output Common Mode Voltage (Si5023) " (CLKOUT)” with updated values. ! Updated Table 3 on page 9. Added “Output Clock Duty Cycle OC-48/12/3” ...
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... Notes: Si5022/Si5023 Rev. 1.23 27 ...
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... Si5022/Si5023 Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...