DS31408GN+ Maxim Integrated Products, DS31408GN+ Datasheet

DS31408GN+

Manufacturer Part Number

DS31408GN+

Description

IC SONET/SDH SYNC CSBGA

Manufacturer

Maxim Integrated Products

Datasheets

1.DS31408.pdf (6 pages)

2.DS31408GN.pdf (6 pages)

3.DS31408GN.pdf (6 pages)

Specifications of DS31408GN+

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

90-31408+GN0

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The DS31408 is a flexible, high-performance timing IC

for diverse frequency conversion and frequency

synthesis applications. On each of its eight input clocks

and fourteen output clocks, the device can accept or

generate nearly any frequency between 2kHz and

750MHz. The device offers two independent DPLLs to

serve two independent clock-generation paths. The

input clocks are divided down, fractionally scaled as

needed, and continuously monitored for activity and

frequency accuracy. The best input clock is selected,

manually or automatically, as the reference clock for

each of the two flexible, high-performance digital PLLs.

Each DPLL lock to the selected reference and provides

programmable bandwidth, very high resolution holdover

capability, and truly hitless switching between input

clocks. The digital PLLs are followed by a clock

synthesis subsystem that has seven fully programmable

digital frequency synthesis blocks, three high-speed

low-jitter APLLs, and 14 output clocks, each with its own

32-bit divider and phase adjustment. The APLLs

provide fractional scaling and output jitter less than 1ps

RMS. For telecom systems, the DS31408 has all

required features and functions to serve as a central

timing function or as a line card timing IC.

In addition the DS31408 has an embedded IEEE 1588

clock that can be steered by system software to follow a

time master elsewhere in the system or elsewhere in

the network. This clock has all necessary features to be

the central time clock in a 1588 ordinary clock,

boundary clock or transparent clock.

Frequency Conversion and IEEE1588 Time/Frequency

Telecom Line Cards or Timing Cards with Any Mix of

+Denotes a lead(Pb)-free/RoHS-compliant package.

SPI is a trademark of Motorola, Inc.

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of

any device may be simultaneously available through various sales channels. For information about device errata, go to:

www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or

visit Maxim’s website at www.maxim-ic.com.

19-5659; Rev 3; 3/11

DS31408GN

DS31408GN+

Applications in a Wide Variety of Equipment Types

SONET/SDH, Synchronous Ethernet and/or OTN

Ports in WAN Equipment Including MSPPs, Ethernet

Switches, Routers, DSLAMs, and Base Stations

PART

-40C to +85C

TEMP RANGE

Ordering Information

with Sub-ps Output Jitter and 1588 Clock

General Description

ABRIDGED DATA SHEET

8-Input, 14-Output, Dual DPLL Timing IC

Applications

PIN-PACKAGE

256 CSBGA



Eight Input Clocks

 Differential or CMOS/TTL Format

 Any Frequency from 2kHz to 750MHz

 Fractional Scaling for 64B/66B and FEC Scaling (e.g.,

 Continuous Input Clock Quality Monitoring

Two High-Performance DPLLs

 Hitless Reference Switching on Loss of Input

 Automatic or Manual Phase Build-Out

 Holdover on Loss of All Inputs

 Programmable Bandwidth, 0.5mHz to 400Hz

Seven Digital Frequency Synthesizers

 Each Can Slave to Either DPLL

 Produce Any 2kHz Multiple Up to 77.76MHz

Three Output APLLs

 Output Frequencies to 750MHz

 High Resolution Fractional Scaling for FEC and

 Less than 1ps RMS Output Jitter

 Simultaneously Produce Three Low-Jitter Rates from

14 Output Clocks in Seven Groups

 Nearly Any Frequency from < 1Hz to 750MHz

 Each Group Slaves to a DFS Clock, Any APLL Clock, or

 Each Has a Differential Output (3 CML, 4 LVDS/

 32-Bit Frequency Divider Per Output

IEEE 1588 Clock Features

 Steerable by Software with 2

 4ns Input Timestamp Accuracy and Output Edge

 Programmable Clock and Time-Alignment I/O to

 Supports 1588 OC, BC, and TC Architectures

General Features

 Suitable Line Card IC or Timing Card IC for Stratum

 Accepts and Produces Nearly Any Frequency from 1Hz

 Internal Compensation for Local Oscillator Frequency Error

 SPI™ Processor Interface

 1.8V Operation with 3.3V I/O (5V Tolerant)

64/66, 237/255, 238/255) or Any Other Downscaling

Requirement

64B/66B (e.g., 255/237, 255/238, 66/64) or Any Other

Scaling Requirement

the Same Reference (e.g., 622.08MHz for SONET,

255/237*622.08MHz for OTU2, and 156.25MHz for

10GE)

Any Input Clock (Divided and Scaled)

LVPECL

Placement Accuracy

Synchronize All 1588 Devices in Large Systems

2/3E/3/4E/4, SMC, SEC/EEC, or SSU

Up to 750MHz

-32

ns Frequency Resolution

) and

Separate CMOS/TTL Output

Maxim Integrated Products 1

-8

ns Time Resolution and

DS31408

Features

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