AD9512BCPZ Analog Devices Inc, AD9512BCPZ Datasheet
AD9512BCPZ
Specifications of AD9512BCPZ
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AD9512BCPZ Summary of contents
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FEATURES Two 1.6 GHz, differential clock inputs 5 programmable dividers 32, all integers Phase select for output-to-output coarse delay adjust 3 independent 1.2 GHz LVPECL outputs Additive output jitter 225 fs rms 2 independent 800 MHz/250 MHz LVDS/CMOS ...
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AD9512 TABLE OF CONTENTS Specifications..................................................................................... 4 Clock Inputs .................................................................................. 4 Clock Outputs ............................................................................... 4 Timing Characteristics ................................................................ 5 Clock Output Phase Noise .......................................................... 7 Clock Output Additive Time Jitter........................................... 10 Serial Control Port ..................................................................... 12 FUNCTION Pin ......................................................................... 13 SYNC ...
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LVPECL Clock Distribution......................................................45 LVDS Clock Distribution...........................................................45 Power and Grounding Considerations and Power Supply Rejection.......................................................................................45 Outline Dimensions........................................................................46 Ordering Guide ...........................................................................46 REVISION HISTORY 6/05—Rev Rev. A Changes to Features ..........................................................................1 Changes to General Description .....................................................1 Changes to Table 1 ............................................................................4 ...
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AD9512 SPECIFICATIONS Typical (Typ) is given for V = 3.3 V ± 5 values are given over full V and T (−40°C to +85°C) variation CLOCK INPUTS Table 1. Parameter 1 CLOCK INPUTS (CLK1, CLK2) Input ...
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TIMING CHARACTERISTICS Table 3. Parameter LVPECL Output Rise Time Output Fall Time PROPAGATION DELAY CLK-TO-LVPECL OUT PECL Divide = Bypass Divide = 2 − 32 Variation with Temperature OUTPUT SKEW, LVPECL OUTPUTS 2 OUT1 ...
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AD9512 Parameter DELAY ADJUST 4 Shortest Delay Range Zero Scale Full Scale Linearity, DNL Linearity, INL 4 Longest Delay Range Zero Scale Full Scale Linearity, DNL Linearity, INL Delay Variation with Temperature 5 Long Delay Range Zero Scale ...
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CLOCK OUTPUT PHASE NOISE Table 4. Parameter CLK1-TO-LVPECL ADDITIVE PHASE NOISE CLK1 = 622.08 MHz, OUT = 622.08 MHz Divide Ratio = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ ...
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AD9512 Parameter CLK1-TO-LVDS ADDITIVE PHASE NOISE CLK1 = 622.08 MHz, OUT = 622.08 MHz Divide Ratio = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 ...
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Parameter CLK1 = 245.76 MHz, OUT = 122.88 MHz Divide Ratio = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset ...
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AD9512 CLOCK OUTPUT ADDITIVE TIME JITTER Table 5. Parameter LVPECL OUTPUT ADDITIVE TIME JITTER CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT2) = 622.08 MHz Divide Ratio = 1 CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT2) = ...
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Parameter CLK1 = 400 MHz LVDS (OUT4) = 100 MHz Divide Ratio = 4 LVDS (OUT3 MHz All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT3) = 100 MHz Divide Ratio = 4 CMOS (OUT4) = ...
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AD9512 Parameter 1 DELAY BLOCK ADDITIVE TIME JITTER 100 MHz Output Delay (1600 μA, 1C) Fine Adj. 00000 Delay (1600 μA, 1C) Fine Adj. 11111 Delay (800 μA, ...
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FUNCTION PIN Table 7. Parameter Min Typ INPUT CHARACTERISTICS Logic 1 Voltage 2.0 Logic 0 Voltage Logic 1 Current 110 Logic 0 Current Capacitance 2 RESET TIMING Pulse Width Low 50 SYNC TIMING Pulse Width Low 1.5 SYNC STATUS PIN ...
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AD9512 POWER Table 9. Parameter POWER-UP DEFAULT MODE POWER DISSIPATION POWER DISSIPATION Full Sleep Power-Down Power-Down (PDB) POWER DELTA CLK1, CLK2 Power-Down Divider, DIV 2 − Bypass LVPECL Output Power-Down (PD2, PD3) LVDS Output Power-Down CMOS Output Power-Down ...
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TIMING DIAGRAMS t CLK1 CLK1 t PECL t LVDS t CMOS Figure 2. CLK1/CLK1B to Clock Output Timing, DIV = 1 Mode DIFFERENTIAL 80% LVPECL 20 Figure 3. LVPECL Timing, Differential DIFFERENTIAL 20% SINGLE-ENDED 20 Rev. ...
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AD9512 ABSOLUTE MAXIMUM RATINGS Table 10. With Respect to Parameter or Pin VS GND DSYNC/DSYNCB GND RSET GND CLK1, CLK1B, CLK2, CLK2B GND CLK1 CLK1B CLK2 CLK2B SCLK, SDIO, SDO, CSB GND OUT0, OUT1, GND OUT2, OUT3, OUT4 FUNCTION GND ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DNC = DO NO CONNECT Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be attached to ...
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AD9512 Table 11. Pin Function Descriptions Pin No. Mnemonic Description 1 DSYNC Detect Sync. Used for multichip synchronization. 2 DSYNCB Detect Sync Complement. Used for multichip synchronization 18, VS Power Supply (3.3 V). 22, 23, 25, ...
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TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 degrees to 360 degrees for each cycle. Actual signals, however, display a certain ...
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AD9512 TYPICAL PERFORMANCE CHARACTERISTICS 0.6 DEFAULT – 3 LVPECL + 2 LVDS (DIV ON) 0.5 3 LVPECL + 2 LVDS (DIV BYPASSED) 0.4 3 LVPECL (DIV ON) 2 LVDS (DIV ON) 0.3 0 400 OUTPUT FREQUENCY (MHz) Figure 7. Power ...
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VERT 500mV/DIV Figure 11. LVPECL Differential Output @ 800 MHz VERT 100mV/DIV Figure 12. LVDS Differential Output @ 800 MHz VERT 500mV/DIV Figure 13. CMOS Single-Ended Output @ 250 MHz with 10 pF Load 1.8 1.7 1.6 1.5 1.4 1.3 ...
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AD9512 –110 –120 –130 –140 –150 –160 –170 10 100 1k 10k OFFSET (Hz) Figure 17. Additive Phase Noise—LVPECL DIV1, 245.76 MHz Distribution Section Only –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 10 100 1k 10k OFFSET ...
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VS GND SYNCB, FUNCTION RESETB PDB PROGRAMMABLE DIVIDERS AND DSYNC PHASE ADJUST DETECT SYNC /1, /2, /3... /31, /32 DSYNCB /1, /2, /3... /31, /32 CLK1 CLK1B /1, /2, /3... /31, /32 CLK2 CLK2B /1, /2, /3... /31, /32 SCLK ...
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AD9512 FUNCTIONAL DESCRIPTION OVERALL Figure 23 shows a block diagram of the AD9512. The AD9512 accepts inputs on either of two clock inputs (CLK1 or CLK2). This clock can be divided by any integer value from 1 to 32. The ...
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DIVIDERS Each of the five clock outputs of the AD9512 has its own divider. The divider can be bypassed to get an output at the same frequency as the input (1×). When a divider is bypassed powered down ...
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AD9512 Divide Ratio Duty Cycle (%) ...
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Divide Ratio Duty Cycle (%) ...
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AD9512 Divide Ratio Duty Cycle (%) 4Ah to 52h Divide Ratio LO<7:4> HI<3:0> ...
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Divider Phase Offset The phase of each output may be selected, depending on the divide ratio chosen. This is selected by writing the appropriate values to the registers, which set the phase and start high/low bit for each output. These ...
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AD9512 DIV = 18 Unique Phase Offsets Are Phase = 10, 11, 12, 13, 14, 15, 16, 17 Phase offsets may be related to degrees by calculating the phase step ...
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Figure 28. LVDS Output Simplified Equivalent Circuit POWER-DOWN MODES Chip Power-Down or Sleep Mode—PDB The PDB chip power-down turns off most of the functions and currents in the AD9512. When the PDB mode is enabled, a chip power-down ...
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AD9512 SINGLE-CHIP SYNCHRONIZATION SYNCB—Hardware SYNC The AD9512 clocks can be synchronized to each other at any time. The outputs of the clocks are forced into a known state with respect to each other and then allowed to continue clocking from ...
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SERIAL CONTROL PORT The AD9512 serial control port is a flexible, synchronous, serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. The AD9512 serial control port is compatible with most synchronous transfer formats, including both ...
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AD9512 writing to Register 5Ah<0> = 1b. This update bit is self-clearing (it is not required to write clear it). Since any number of bytes of data can be changed before issuing an update command, the ...
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Table 15. Serial Control Port, 16-Bit Instruction Word, MSB First MSB I15 I14 I13 I12 I11 A12 = 0 A11 = 0 CSB SCLK DON’T CARE SDIO R A12 A11 A10 ...
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AD9512 t S CSB t DS SCLK SDIO BI N Table 16. Serial Control Port Timing Parameter Description t Setup time between data and rising edge of SCLK DS t Hold time between data and rising edge of SCLK DH ...
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REGISTER MAP AND DESCRIPTION SUMMARY TABLE Table 17. AD9512 Register Map Addr (Hex) Parameter Bit 7 (MSB) 00 Serial SDO Inactive Control Port (Bidirectional Configuration Mode FINE DELAY ADJUST 34 Delay Bypass 4 35 Delay Not Used ...
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AD9512 Addr (Hex) Parameter Bit 7 (MSB) 4F Divider 2 Bypass 50 Divider 3 51 Divider 3 Bypass 52 Divider 4 53 Divider 4 Bypass 54, 55, 56, 57 FUNCTION 58 FUNCTION Not Pin and Sync Used 59 5A Update ...
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REGISTER MAP DESCRIPTION Table 18 lists the AD9512 control registers by hexadecimal address. A specific bit or range of bits within a register is indicated by angle brackets. For example, <3> refers to Bit 3, while <5:2> refers to the ...
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AD9512 Reg. Addr. (Hex) Bit(s) Name 36 <5:1> Delay Fine Adjust OUT4 36 <7:6> 37 (38) <7:0> (39) (3A) (3B) (3C) OUTPUTS 3D (3E) <1:0> Power-Down LVPECL (3F) OUT0 (OUT1) (OUT2) 3D (3E) <3:2> Output Level LVPECL (3F) OUT0 (OUT1) ...
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Reg. Addr. (Hex) Bit(s) Name CLK1 AND CLK2 45 <0> Clock Select 45 <1> CLK1 Power-Down 45 <2> CLK2 Power-Down 45 <4:3> 45 <5> All Clock Inputs Power- Down 45 <7:6> 46 (47) <7:0> (48) (49) DIVIDERS <3:0> Divider High ...
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AD9512 Reg. Addr. (Hex) Bit(s) Name <7> Bypass Divider 4B OUT0 (4D) (OUT1) (4F) (OUT2) (51) (OUT3) (53) (OUT4) 54 (55) <7:0> (56) (57) FUNCTION 58 <0> SYNC Detect Enable 58 <1> SYNC Select 58 <2> Soft SYNC 58 <3> ...
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POWER SUPPLY The AD9512 requires a 3.3 V ± 5% power supply for V The tables in the Specifications section give the performance expected from the AD9512 with the power supply voltage within this range. The absolute maximum range of ...
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AD9512 APPLICATIONS USING THE AD9512 OUTPUTS FOR ADC CLOCK APPLICATIONS Any high speed analog-to-digital converter (ADC) is extremely sensitive to the quality of the sampling clock provided by the user. An ADC can be thought sampling mixer; ...
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Because of the limitations of single-ended CMOS clocking, consider using differential outputs when driving high speed signals over long traces. The AD9512 offers both LVPECL and LVDS outputs, which are better suited for driving long traces where the inherent noise ...
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... PIN 1 INDICATOR TOP VIEW 1.00 12° MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 AD9512BCPZ −40°C to +85°C 1 AD9512BCPZ-REEL7 −40°C to +85°C AD9512/PCB Pb-free part. 0.60 MAX 37 36 6.75 BSC SQ 0.50 0. 0.30 0.80 MAX 0.65 TYP 0.05 MAX ...
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NOTES Rev Page AD9512 ...
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AD9512 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05287–0–6/05(A) Rev Page ...