MAX9316EWP Maxim Integrated Products, MAX9316EWP Datasheet
MAX9316EWP
Specifications of MAX9316EWP
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MAX9316EWP Summary of contents
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... Output-to-Output Skew o 365ps Propagation Delay o Synchronous Output Enable/Disable o On-Chip Reference for Single-Ended Inputs o Input Biased to Low when Open o Pin Compatible with MC100LVEL14 PART Applications MAX9316EUP MAX9316EWP* *Future product—contact factory for availability. TOP VIEW RECEIVER 50Ω - 2.0V Features Ordering Information TEMP. RANGE PIN-PACKAGE -40° ...
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Differential LVPECL/LVECL/HSTL Clock and Data Driver ABSOLUTE MAXIMUM RATINGS ...............................................................................4. Inputs (CLK, CLK, SCLK, SEL, EN ...........................................( CLK to CLK ........................................................................±3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA V Sink/Source ...
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Differential LVPECL/LVECL/HSTL DC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.8V, outputs loaded with 50Ω ± values are +3.3V IHD PARAMETER SYMBOL CONDITIONS ...
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Differential LVPECL/LVECL/HSTL Clock and Data Driver AC ELECTRICAL CHARACTERISTICS ( +3.0V to +3.8V, outputs are loaded with 50Ω ± (20% to 80%), SEL = high or low low, V otherwise ...
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Differential LVPECL/LVECL/HSTL (V = +3.3V 1V IHD CC ILD 50Ω 2V +25°C, unless otherwise noted SUPPLY CURRENT vs.TEMPERATURE 40 ALL PINS ARE OPEN EXCEPT ...
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Differential LVPECL/LVECL/HSTL Clock and Data Driver PIN NAME 1 Q0 Noninverting Q0 Output. Typically terminate with 50Ω resistor Inverting Q0 Output. Typically terminate with 50Ω resistor Noninverting Q1 Output. Typically terminate ...
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Differential LVPECL/LVECL/HSTL ed), allowing high-performance clock or data distribu- tion in systems with a nominal +3.3V supply. For inter- facing to differential LVECL, the V -3.8V (with V grounded). Output levels are refer- CC enced to V and are ...
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Differential LVPECL/LVECL/HSTL Clock and Data Driver CLK CLK Q_ Q_ Figure 1. MAX9316 Switching Characteristics with Single-Ended Input CLK CLK Figure 2. MAX9316 Timing Diagram 8 _______________________________________________________________________________________ ...
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Differential LVPECL/LVECL/HSTL SCLK Figure 3. MAX9316 Timing Diagram for SCLK CLK SCLK OR CLK Q_ OUTPUTS ARE LOW Q_ Figure 4. MAX9316 EN Timing Diagram _______________________________________________________________________________________ Clock and Data Driver t ...
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Differential LVPECL/LVECL/HSTL Clock and Data Driver V CC 75kΩ CLK CLK 75kΩ 75kΩ SCLK 75kΩ SEL ______________________________________________________________________________________ 60kΩ 60kΩ ...
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Differential LVPECL/LVECL/HSTL ______________________________________________________________________________________ Clock and Data Driver Package Information 11 ...
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... Maxim reserves the right to change the circuitry and specifications without notice at any time. implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © ...