NBSG14MN ON Semiconductor, NBSG14MN Datasheet - Page 2

• Manufacturer Part Number: NBSG14MN
• Description: IC DRIVER CLOCK RSECL 1:4 16QFN
• Manufacturer: ON Semiconductor
• Type: Fanout Buffer (Distribution), Datar

Specifications of NBSG14MN

• Number Of Circuits: 1
• Ratio - Input:output: 1:4
• Differential - Input:output: Yes/Yes
• Input: CML, LVCMOS, LVDS, LVTTL, NECL, PECL, RSECL
• Output: RSECL, RSNECL, RSPECL
• Frequency - Max: 12GHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TFQFN Exposed Pad
• Frequency-max: 12GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: NBSG14MNOS

Table 1. Pin Description
1. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage, if no
*Devices in BGA package typically terminated with 50 W to V
B2,C2
B3,C3
BGA
A2*
A3*
A4*
B4*
C4*
D4*
D3*
D2*
N/A
D1
C1
B1
A1
signal is applied then the device will be susceptible to self−oscillation.
Pin
Figure 1. BGA−16 Pinout (Top View)
C
D
A
B
QFN
5,16
8,13
10
12
14
15
11
1
2
3
4
6
7
9
−
VTCLK
VTCLK
CLK
CLK
1
VTCLK
VTCLK
Name
CLK
CLK
V
V
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
EP
EE
CC
VEE
VEE
Q3
Q0
2
LVCMOS, LVDS,
LVCMOS, LVDS,
RSECL Output
RSECL Output
RSECL Output
RSECL Output
RSECL Output
RSECL Output
RSECL Output
RSECL Output
VCC
VCC
Q3
Q0
3
LVTTL Input
LVTTL Input
ECL, CML,
ECL, CML,
I/O
−
−
−
−
−
4
Q2
Q2
Q1
Q1
Internal 50 W Termination pin. See Table 2.
Inverted Differential Input. Internal 75 kW to V
Noninverted Differential Input. Internal 75 kW to VEE.
Internal 50 W Termination Pin. See Table 2.
Negative Supply Voltage. All V
Supply to Guarantee Proper Operation.
Inverted Differential Output 3. Typically Terminated with 50 W to V
Noninverted Differential Output 3. Typically Terminated with 50 W to
V
Positive Supply Voltage. All V
Supply to Guarantee Proper Operation.
Inverted Differential Output 2. Typically Terminated with 50 W to V
Noninverted Differential Output 2. Typically Terminated with 50 W to
V
Inverted Differential Output 1. Typically Terminated with 50 W to V
Noninverted Differential Output 1. Typically Terminated with 50 W to
V
Inverted Differential Output 0. Typically Terminated with 50 W to V
Noninverted Differential Output 0. Typically Terminated with 50 W to
V
The Exposed Pad (EP) and the QFN−16 package bottom is thermally connected
to the die for improved heat transfer out of package. The exposed pad must be
attached to a heat−sinking conduit. The pad is not electrically connected to the die
but may be electrically and thermally connected to V
TT
TT
TT
TT
http://onsemi.com
= V
= V
= V
= V
VTCLK
VTCLK
TT
CC
CC
CC
CC
CLK
CLK
= V
− 2 V*
− 2 V*
− 2 V*
− 2 V*
CC
2
Figure 2. QFN−16 Pinout (Top View)
− 1.5 V.
1
2
3
4
V
V
16
EE
5
EE
Q0
15
Q3
NBSG14
CC
6
EE
Pins must be Externally Connected to Power
Pins must be Externally Connected to Power
Description
Q0
14
Q3
7
V
V
13
8
CC
CC
EE
and 36.5 kW to V
12
10
11
9
EE
Q1
Q1
Q2
Q2
on the PC board.
Exposed Pad (EP)
CC
TT
TT
TT
TT
.
= V
= V
= V
= V
CC
CC
CC
CC
− 2 V*
− 2 V*
− 2 V*
− 2 V*