CY22150KFZXC Cypress Semiconductor Corp, CY22150KFZXC Datasheet - Page 12

• Manufacturer Part Number: CY22150KFZXC
• Description: IC CLOCK GEN PROG FLASH 16-TSSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Generator, Fanout Distributionr

Specifications of CY22150KFZXC

• Number Of Circuits: 1
• Package / Case: 16-TSSOP
• Pll: Yes
• Input: Crystal
• Output: Clock
• Ratio - Input:output: 1:6
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 200MHz
• Maximum Input Frequency: 133 MHz
• Minimum Input Frequency: 1 MHz
• Output Frequency Range: 0.08 MHz to 200 MHz
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Number Of Elements: 1
• Supply Current: 45mA
• Pll Input Freq (min): 1MHz
• Pll Input Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSSOP
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY30700 - KIT PROG FOR CY22150
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

AC Electrical Characteristics
Device Characteristics
Document #: 38-07104 Rev. *I
Parameter
Complexity
Parameter
t2
t3
t4
t5
t6
t2
t3
t4
t10
t1
LO
LO
LO
[8]
[9]
HI
HI
HI
θ
JA
[7]
Output Frequency,
Commercial Temp
Output Frequency,
Industrial Temp
Output Duty Cycle
Output Duty Cycle
Rising Edge Slew
Rate (V
Falling Edge Slew
Rate (V
Rising Edge Slew
Rate (V
Falling Edge Slew
Rate (V
Skew
Clock Jitter
PLL Lock Time
DDL
DDL
DDL
DDL
Name
= 2.5V)
= 2.5V)
= 3.3V)
= 3.3V)
Transistor Count
Theta JA
Name
Clock output limit, 3.3V
Clock output limit, 2.5V
Clock output limit, 3.3V
Clock output limit, 2.5V
Duty cycle is defined in
t1/t2
fOUT < 166 MHz, 50% of V
Duty cycle is defined in
fOUT > 166 MHz, 50% of V
Output clock rise time, 20% to 80% of V
Defined in
Output dlock fall time, 80% to 20% of V
Defined in
Output dlock rise time, 20% to 80% of
V
Output dlock fall time, 80% to 20% of V
Defined in
Output-output skew between related outputs
Peak-to-peak period jitter
DD
/V
DDL
. Defined in
Figure 9
Figure 9
Figure 9
Description
Figure 9
Figure 8
Figure
DD
DD
8; t1/t2
74,600
Value
on page 10;
115
DD
DDL
DDL
/V
DDL
.
.
.
0.08 (80 kHz)
0.08 (80 kHz)
0.08 (80 kHz)
0.08 (80 kHz)
Min
0.6
0.6
0.8
0.8
45
40
Typ.
0.30
250
1.2
1.2
1.4
1.4
50
50
Transistors
°C/W
Unit
166.6
166.6
Max
200
150
250
CY22150
55
60
3
Page 12 of 16
Unit
MHz
MHz
MHz
MHz
V/ns
V/ns
V/ns
V/ns
ms
ps
ps
%
%
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