CY23EP05SXC-1H Cypress Semiconductor Corp, CY23EP05SXC-1H Datasheet
CY23EP05SXC-1H
Specifications of CY23EP05SXC-1H
CY23EP05SXC-1H
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CY23EP05SXC-1H Summary of contents
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... Industrial temperature available Block Diagram PLL REF Cypress Semiconductor Corporation Document #: 38-07759 Rev. *B Functional Description The CY23EP05 is a 2.5V or 3.3V zero delay buffer designed to distribute low-jitter high-speed clocks and is available in a 8-pin SOIC package. It accepts one reference input, and drives out five low-skew clocks ...
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Pin Description Pin Signal [1] 1 REF [2] 2 CLK2 [2] 3 CLK1 4 GND [2] 5 CLK3 [2] 7 CLK4 [2,3] 8 CLKOUT Zero Delay and Skew Control All outputs should be uniformly loaded to achieve ...
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Absolute Maximum Conditions Supply Voltage to Ground Potential ................. –0.5V to 4.6V DC Input Voltage...................................... V Operating Conditions Parameter V 3.3V Supply Voltage DD3.3 V 2.5V Supply Voltage DD2.5 T Operating Temperature (Ambient Temperature)—Commercial A Operating Temperature (Ambient Temperature)—Industrial [4] ...
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DC Electrical Specifications Parameter Description V Supply Voltage DD V Input LOW Voltage IL V Input HIGH Voltage IH I Input Leakage Current IL I Input HIGH Current IH V Output LOW Voltage OL V Output HIGH Voltage OH ...
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AC Electrical Specifications Parameter Description [8] t PLL Lock Time LOCK [8,9] T Cycle-to-cycle Jitter, Peak 3.3V supply, >66 MHz, <15 pF JCC [8,9] T Period Jitter, Peak PER Switching Waveforms 2.0V(1.8V) OUTPUT 0.8V(0.6V OUTPUT ...
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Switching Waveforms (continued) V INPUT CLKOUT t 6 Any output, Part Any output, Part Test Circuits Test Circuit # CLK 0.1 µ F OUTPUTS V DD 0.1 µ F GND GND ...
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Supplemental Parametric Information Figure 1. 2.5V Typical Room Temperature Graph for REF Input to CLKn Delay versus Loading Difference between CLKOUT and CLKn. Data is shown for 66 MHz. Delay is a weak function of frequency. Figure 2. 3.3V Typical ...
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Figure 3. 2.7V Measured Supply Current versus Frequency, Drive Strength, Loading, and Temperature. Note that the 30-pF data above 100 MHz is beyond the data sheet specification of 22 pF. ...
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Figure 5. Typical 3.3V Measured Cycle-to-cycle Jitter at 29°C, versus Frequency, Drive Strength, and Loading 400 350 300 250 200 150 100 Figure 6. Typical 2.5V Measured ...
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MHz 100 MHz 100 MHz -140 -140 -140 1.E+01 1.E+01 1.E+01 1.E+02 1.E+02 1.E+02 1.E+03 1.E+03 1.E+03 -90 -90 -90 -100 -100 -100 -110 ...
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... SOIC – Tape and Reel CY23EP05SXI-1 8-pin 150-mil SOIC CY23EP05SXI-1T 8-pin 150-mil SOIC – Tape and Reel CY23EP05SXC-1H 8-pin 150-mil SOIC CY23EP05SXC-1HT 8-pin 150-mil SOIC – Tape and Reel CY23EP05SXI-1H 8-pin 150-mil SOIC CY23EP05SXI-1HT 8-pin 150-mil SOIC – Tape and Reel Package Drawing and Dimensions ...
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... See ECN *A 401073 See ECN *B 413826 See ECN Document #: 38-07759 Rev. *B Orig. of Change Description of Change RGL New data sheet RGL Updated Delay vs. Load graph with standard drive data Added Phase-noise graph RGL Minor Change: typo - changed from CY23EP05SXC-T to CY23EP05SXC-1T CY23EP05 Page [+] Feedback ...