CY22394FXI Cypress Semiconductor Corp, CY22394FXI Datasheet - Page 4

• Manufacturer Part Number: CY22394FXI
• Description: IC CLOCK GEN PROG 16-TSSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Generator, Fanout Distributionr

Specifications of CY22394FXI

• Number Of Circuits: 1
• Package / Case: 16-TSSOP
• Pll: Yes
• Input: Crystal
• Output: CMOS, PECL
• Ratio - Input:output: 1:5
• Differential - Input:output: No/Yes
• Frequency - Max: 166MHz, 375MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 375MHz
• Maximum Input Frequency: 150 MHz
• Minimum Input Frequency: 1 MHz
• Output Frequency Range: 125 MHz to 375 MHz
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-1918 - KIT DEV FTG PROGRAMMING KIT428-1455 - SOCKET ADAPTER FOR CY2239X
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2181-5; CY22394FXI

Document #: 38-07186 Rev. *B
Pin Definitions
Operation
The CY22393, CY22394, and CY22395 are a family of parts
designed as upgrades to the existing CY22392 device. These
parts have similar performance to the CY22392, but provide
advanced features to meet the needs of more demanding
applications.
The clock family has three PLLs which, when combined with
the reference, allow up to four independent frequencies to be
output on up to six pins. These three PLLs are completely
programmable.
Configurable PLLs
PLL1 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL1 is sent
to two locations: the cross point switch and the PECL output
(CY22394). The output of PLL1 is also sent to a /2, /3, or /4
synchronous post-divider that is output through CLKE. The
frequency of PLL1 can be changed via serial programming or
by external CMOS inputs, S0, S1, and S2. See the following
section on general-purpose Inputs for more detail.
PLL2 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL2 is sent
to the cross point switch. The frequency of PLL2 can be
changed via serial programming.
PLL3 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL3 is sent
to the cross point switch. The frequency of PLL3 can be
changed via serial programming.
General-Purpose Inputs
S2 is a general-purpose input that can be programmed to
allow for two different frequency settings. Options that may be
switched with this general-purpose input are as follows: the
frequency of PLL1, the output divider of CLKB, and the output
divider of CLKA.
The two frequency settings are contained within an eight-row
frequency table. The values of SCLK (S1) and SDAT (S0) pins
are latched during start-up and used as the other two indexes
into this array.
CLKA or LCLKA
GND/LGND
SDAT (S0)
SCLK (S1)
AV
S2/
SUSPEND
SHUTDOWN/
OE
DD
Name
(continued)
Pin Number
CY22393
10
12
13
14
15
16
11
Pin Number
CY22394
10
11
12
13
14
15
16
Pin Number
CY22395
10
11
12
13
14
15
16
Configurable clock output A; LCLKA referenced to LVDD
Ground
Two Wire Serial Port Data. S0 value latched during start-up
Two Wire Serial Port Clock. S1 value latched during start-up
Analog Power Supply
General Purpose Input for Frequency Control; bit 2. Optionally
Suspend mode control input
Places outputs in three-state condition and shuts down chip
when LOW. Optionally, only places outputs in three-state
condition and does not shut down chip when LOW
CLKA and CLKB both have 7-bit dividers that point to one of
two programmable settings (register 0 and register 1). Both
clocks share a single register control, so both must be set to
register 0, or both must be set to register 1.
For example, the part may be programmed to use S0, S1, and
S2 (0,0,0 to 1,1,1) to control eight different values of P and Q
on PLL1. For each PLL1 P and Q setting, one of the two CLKA
and CLKB divider registers can be chosen. Any divider change
as a result of switching S0, S1, or S2 is guaranteed to be glitch
free.
Crystal Input
The input crystal oscillator is an important feature of this family
of parts because of its flexibility and performance features.
The oscillator inverter has programmable drive strength. This
allows for maximum compatibility with crystals from various
manufacturers, process, performance, and quality.
The input load capacitors are placed on-die to reduce external
component cost. These capacitors are true parallel-plate
capacitors for ultra-linear performance. These were chosen to
reduce the frequency shift that occurs when non-linear load
capacitance interacts with load, bias, supply, and temperature
changes. Non-linear (FET gate) crystal load capacitors should
not be used for MPEG, POTS dial tone, communications, or
other applications that are sensitive to absolute frequency
requirements.
The value of the load capacitors is determined by six bits in a
programmable register. The load capacitance can be set with
a resolution of 0.375 pF for a total crystal load range of 6 pF
to 30 pF.
For driven clock inputs the input load capacitors may be
completely bypassed. This enables the clock chip to accept
driven frequency inputs up to 166 MHz. If the application
requires a driven input, then XTALOUT must be left floating.
Digital VCXO
The serial programming interface may be used to dynamically
change the capacitor load value on the crystal. A change in
crystal load capacitance corresponds with a change in the
reference frequency.
For special pullable crystals specified by Cypress, the capac-
itance pull range is +150 ppm to –150 ppm from midrange.
Description
CY22393
CY22394
CY22395
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