ICS8735AY-31LF IDT, Integrated Device Technology Inc, ICS8735AY-31LF Datasheet
ICS8735AY-31LF
Specifications of ICS8735AY-31LF
8735AY-31LF
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ICS8735AY-31LF Summary of contents
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... Q2 nQ2 1 Q3 nQ3 Q4 PLL nQ4 1 ICS8735-31 Pin Assignment SEL0 1 2 SEL1 3 CLK0 nCLK0 4 5 CLK1 6 nCLK1 CLK_SEL ICS8735-31 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View ICS8735AY-31 REV. B FEBRUARY 18, 2009 24 V CCO Q3 23 nQ3 nQ2 Q1 19 nQ1 CCO ...
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... Analog supply pin. PLL select. Selects between the PLL and reference clock as the input to the Pullup dividers. When LOW, selects reference clock. When HIGH, selects PLL. LVCMOS/LVTTL interface levels. Test Conditions 2 Minimum Typical Maximum ICS8735AY-31 REV. B FEBRUARY 18, 2009 Units pF Ω k Ω k ...
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... Outputs PLL_SEL = 1 PLL Enable Mode Q0:Q4, nQ0:nQ4 ÷1 ÷1 ÷1 ÷1 ÷2 ÷2 ÷2 ÷4 ÷4 ÷ ICS8735AY-31 REV. B FEBRUARY 18, 2009 ...
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... SEL3 SEL2 SEL1 IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR Outputs PLL_SEL = 0 PLL Bypass Mode SEL0 Q0:Q4, nQ0:nQ4 0 ÷8 1 ÷8 0 ÷8 1 ÷16 0 ÷16 1 ÷16 0 ÷32 1 ÷32 0 ÷64 1 ÷128 0 ÷4 1 ÷4 0 ÷8 1 ÷2 0 ÷4 1 ÷2 4 ICS8735AY-31 REV. B FEBRUARY 18, 2009 ...
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... V = 3.465V 3.465V 3.465V 0. 0V 0°C to 70° Typical Maximum 3.3 3.465 3.3 3.465 3.3 3.465 150 0°C to 70° Minimum Typical Maximum 0.3 CC -0.3 0.8 150 5 -5 -150 ICS8735AY-31 REV. B FEBRUARY 18, 2009 Units Units V V µA µA µA µA ...
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... EE A Minimum Typical Maximum V – 1.4 V – 0.9 CCO CCO V – 2.0 V – 1.7 CCO CCO 0.6 1 0°C to 70° Minimum Typical Maximum 15.625 350 700 ICS8735AY-31 REV. B FEBRUARY 18, 2009 Units µA µA µA µ Units Units MHz MHz ...
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... IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR = 3.3V ± 5 0V, T CCA CCO EE Test Conditions PLL_SEL = 0, f ≤ 350MHz PLL_SEL = 1 20 0°C to 70°C A Minimum Typical Maximum 350 3.8 5.1 35 -70 55 +180 60 1 200 750 47 53 ICS8735AY-31 REV. B FEBRUARY 18, 2009 Units MHz ...
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... IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR SCOPE Qx nQx Differential Input Level V nQx nQy Output Skew nQ[0:4] ➤ ➤ tcycle n+1 Q[0:4] | Output Rise/Fall Time nCLK0, nCLK1 V Cross Points PP CLK0, CLK1 V EE tsk(o) 80% 80% 20 ICS8735AY-31 REV. B FEBRUARY 18, 2009 V CMR 20 ...
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... IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR nCLK0, nCLK1 CLK0, CLK1 nQ[0:4] x 100% Q[0:4] Propagation Delay Outputs: LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated ICS8735AY-31 REV. B FEBRUARY 18, 2009 ...
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... IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR and V should be CCA CCO CCA / Figure 2. Single-Ended Signal Driving Differential Input 10 3. .01µF 10Ω V CCA .01µF 10µF Figure 1. Power Supply Filtering Single Ended Clock Input CLKx V_REF nCLKx C1 0. ICS8735AY-31 REV. B FEBRUARY 18, 2009 ...
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... Zo = 50Ω R1 100 Zo = 50Ω LVDS Driven by a 3.3V LVDS Driver 2. 120 120 Zo = 60Ω 60Ω SSTL R1 R2 120 120 Driven by a 2.5V SSTL Driver ICS8735AY-31 REV. B FEBRUARY 18, 2009 3.3V CLK nCLK HiPerClockS Input 3.3V CLK nCLK Receiver 3.3V CLK nCLK HiPerClockS ...
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... FIN FOUT 50Ω RTT Figure 4B. 3.3V LVPECL Output Termination 12 3.3V 125Ω 125Ω 50Ω o FIN Z = 50Ω o 84Ω 84Ω ICS8735AY-31 REV. B FEBRUARY 18, 2009 ...
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... VCC 10 C16 10u (77.76 MHz Ohm Ohm Bypass capacitor located near the power pins (U1-9) (U1-32) VCC C1 C6 0.1uF 0.1uF (U1-16) (U1-17) (U1-24) VCCO C2 C4 0.1uF 0.1uF ICS8735AY-31 REV. B FEBRUARY 18, 2009 + - LVPECL_input R4 50 Output Termination Example VCC=3.3V VCCO=3.3V (U1-25 0.1uF 0.1uF ...
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... Make sure no other signal traces are routed between the clock trace pair. • The matching termination resistors should be located as close to the receiver input pins as possible GND VCCO VCC VCCA VIA 50 Ohm Traces ICS8735AY-31 REV. B FEBRUARY 18, 2009 ...
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... 3.465V * 150mA = 519.75mW CC_MAX * Pd_total + for 32 Lead LQFP, Forced Convection θ vs. Air Flow JA 0 67.8°C/W 47.9°C/W 15 must be used. Assuming no air flow JA 200 500 55.9°C/W 50.1°C/W 42.1°C/W 39.4°C/W ICS8735AY-31 REV. B FEBRUARY 18, 2009 ...
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... IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR V OUT RL 50Ω CCO = V – 0.9V CCO_MAX = V – 1.7V CCO_MAX ] * (V – [(2V – CCO_MAX OH_MAX ] * (V – [(2V – CCO_MAX OL_MAX 16 – V ))/ CCO_MAX OH_MAX L CCO_MAX – V ))/ CCO_MAX OL_MAX L CCO_MAX ICS8735AY-31 REV. B FEBRUARY 18, 2009 – OH_MAX – OL_MAX ...
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... NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Transistor Count The transistor count for ICS8735-31 is: 2969 IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR θ vs. Air Flow JA 0 200 67.8°C/W 55.9°C/W 47.9°C/W 42.1°C/W 17 ICS8735AY-31 REV. B FEBRUARY 18, 2009 500 50.1°C/W 39.4°C/W ...
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... D1 & E1 7.00 Basic D2 & E2 5.60 Ref. e 0.80 Basic L 0.45 0.60 θ 0° ccc Reference Document: JEDEC Publication 95, MS-026 IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR Maximum 1.60 0.15 1.45 0.45 0.20 0.75 7° 0.10 18 ICS8735AY-31 REV. B FEBRUARY 18, 2009 ...
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... Shipping Packaging 32 Lead LQFP 32 Lead LQFP 1000 Tape & Reel “Lead-Free” 32 Lead LQFP “Lead-Free” 32 Lead LQFP 1000 Tape & Reel 19 Temperature Tray 0°C to 70°C 0°C to 70°C Tray 0°C to 70°C 0°C to 70°C ICS8735AY-31 REV. B FEBRUARY 18, 2009 ...
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... Ordering Information Table - deleted “ICS” from Part/Order Number. 1 Pin Assignment -due to format conversion dated February 11, 2008 datasheet, B corrected typo on pin 19 from nQ1 to Q1 and, pin 10 from FB_IN to nFB_IN. IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR 20 ICS8735AY-31 REV. B FEBRUARY 18, 2009 Date 12/19/07 2/11/08 2/18/09 ...
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ICS8735-31 1:5, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT © 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are ...