CY7B9911V-5JXC Cypress Semiconductor Corp, CY7B9911V-5JXC Datasheet
CY7B9911V-5JXC
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CY7B9911V-5JXC
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CY7B9911V-5JXC Summary of contents
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... Document Number: 38-07408 Rev. *F High Speed Low Voltage Programmable Functional Description The CY7B9911V 3.3 V RoboClock+™ High Speed Low Voltage Programmable Skew Clock Buffer (LVPSCB) offers user selectable control over system clock functions. These multiple output clock drivers provide the system integrator with functions necessary to optimize the timing of high performance computer systems ...
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... Document Number: 38-07408 Rev. *F 3.3 V RoboClock+™ Switching Characteristics .............................................. 11 AC Timing Diagrams ...................................................... 12 Ordering Information ...................................................... 13 Ordering Code Definitions ......................................... 13 Package Diagram ............................................................ 14 Acronyms ........................................................................ 15 Document Conventions ................................................. 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 17 Worldwide Sales and Design Support ....................... 17 Products .................................................................... 17 PSoC Solutions ......................................................... 17 CY7B9911V Page [+] Feedback ...
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... GND 12 22 GND Description Table 1. “Test Mode” on page 5 under the Table 2. Table 2. Table 2. Table 2. CY7B9911V 3.3 V RoboClock+™ 2F0 GND 1F1 1F0 V CCN 1Q0 1Q1 GND GND Table 2. Table 2. Table 2. Table 2. “Block Diagram Description” on page 4. Page [+] Feedback ...
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... LOW indicates a connection to GND, and MID indicates an open connection. Internal termination the V and Time Unit Generator NOM CO has reached 2 CY7B9911V 3.3 V RoboClock+™ Table 2 shows the nine possible output [1] Output Functions 1Q0, 1Q1, 3Q0, 3Q1 4Q0, 4Q1 3F0, 4F0 2Q0, 2Q1 – ...
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... INVERT Test Mode The TEST input is a three level input. In normal system operation, this pin is connected to ground, allowing the CY7B9911V to operate as described in “Block Diagram Description” on page 4. For testing purposes, any of the three level inputs can have a removable jumper to ground or be tied LOW through a 100Ω ...
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... Figure 2 shows the LVPSCB configured as a zero skew clock buffer. In this mode the CY7B9911V is used as the basis for a low skew clock distribution tree. When all the function select inputs (xF0, xF1) are left open, each of the outputs are aligned and drive a terminated transmission line to an independent load ...
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... Without this feature MHz external divider is added, and the propagation delay of the divider adds to the skew between the different clock signals. CY7B9911V 3.3 V RoboClock+™ ⁄ ⁄ 1 ...
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... TEST Figure 8 shows the CY7B9911V connected in series to construct a zero skew clock distribution tree between boards. Delays of the downstream clock buffers are programmed to compensate for the wire length (that is, select negative skew equal to the wire delay) necessary to connect them to the master clock source, approximating a zero delay clock tree. Cascaded clock buffers accumulates low frequency jitter because of the non-ideal filtering characteristics of the PLL filter ...
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... CY7B9911V must be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. 8. Total output current per output pair is approximated by the following expression that includes device current plus load current: CY7B9911V: ICCN = [(4 + 0.11F) + [[((835 – ...
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... Applies to REF and FB inputs only. Document Number: 38-07408 Rev. *F Test Conditions T = 25° MHz 3 Figure 9. AC Test Loads and Waveforms 2 =1 0.8 V 0.0 V ≤1ns TTL Input Test Waveform CY7B9911V 3.3 V RoboClock+™ [10] Max Unit 10 pF 3 0.8 V ≤1ns Page [+] Feedback ...
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... JR Jitter Notes 11. Test measurement levels for the CY7B9911V are TTL levels (1 1.5 V). Test conditions assume signal transition times less and output loading as shown in the AC Test Loads and Waveforms 12. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. ...
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... AC Timing Diagrams REF OTHER Q INVERTED Q REF DIVIDED BY 2 REF DIVIDED BY 4 Document Number: 38-07408 Rev REF RPWL t RPWH t ODCV t ODCV t t SKEWPR, SKEWPR SKEW0,1 SKEW0,1 t SKEW2 t SKEW3,4 t SKEW3,4 t SKEW1,3, 4 CY7B9911V 3.3 V RoboClock+™ SKEW2 t SKEW3,4 t SKEW2,4 Page [+] Feedback ...
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... Ordering Code CY7B9911V-5JC 32-Pin Plastic Leaded Chip Carrier CY7B9911V-5JCT 32-Pin Plastic Leaded Chip Carrier – Tape and Reel Pb-free CY7B9911V-5JXC 32-Pin Plastic Leaded Chip Carrier CY7B9911V-5JXCT 32-Pin Plastic Leaded Chip Carrier – Tape and Reel Ordering Code Definitions CY 7B9911V J X C/I ...
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... Package Diagram Figure 10. 32-Pin Plastic Leaded Chip Carrier J65 Document Number: 38-07408 Rev. *F CY7B9911V 3.3 V RoboClock+™ 51-85002 *C Page [+] Feedback ...
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... Document Number: 38-07408 Rev. *F 3.3 V RoboClock+™ Document Conventions Table 4. Units of Measure Symbol Unit of Measure °C degree Celsius kΩ kilo ohm µA microamperes µs microsecond mA milliamperes ms millisecond mW milliwatt MHz megahertz ns nanosecond Ω ohm pF pico Farad ps pico second V volts W watts CY7B9911V Page [+] Feedback ...
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... Document History Page Document Title: CY7B9911V 3.3 V RoboClock+™ High Speed Low Voltage Programmable Skew Clock Buffer Document Number: 38-07408 Orig. of Submission Revision ECN Change ** 114350 DSG *A 299713 RGL *B 404630 RGL *C 1199925 KVM/AESA *D 1286064 AESA *E 2894960 KVM *F 3218954 BASH Document Number: 38-07408 Rev. *F ...
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... Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-07408 Rev. *F All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised April 7, 2011 CY7B9911V 3.3 V RoboClock+™ PSoC Solutions psoc.cypress.com/solutions PSoC 1 ...