CY7B991-5JI Cypress Semiconductor Corp, CY7B991-5JI Datasheet - Page 9

• Manufacturer Part Number: CY7B991-5JI
• Description: IC CLK BUFF SKEW 8OUT 32PLCC
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Zero Delay Bufferr

Specifications of CY7B991-5JI

• Number Of Circuits: 1
• Package / Case: 32-PLCC
• Pll: Yes
• Input: TTL
• Output: TTL
• Ratio - Input:output: 1:4
• Differential - Input:output: No/No
• Frequency - Max: 80MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 80MHz
• Output Frequency Range: 3.75 MHz to 80 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Switching Characteristics
Over the Operating Range
Document Number: 38-07138 Rev. *E
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes
NOM
RPWH
RPWL
U
SKEWPR
SKEW0
SKEW1
SKEW2
SKEW3
SKEW4
DEV
PD
ODCV
PWH
PWL
ORISE
OFALL
LOCK
JR
Parameter
12. CMOS output buffer current and power dissipation specified at 50 MHz reference frequency.
13. Test measurement levels for the CY7B991 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B992 are CMOS levels (VCC/2 to VCC/2). Test
14. Guaranteed by statistical correlation. Tested initially and after any design or process changes that affect these parameters.
15. Except as noted, all CY7B992–2 and –5 timing parameters are specified to 80 MHz with a 30 pF load.
16. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay is selected when all are loaded
17. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.
18. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.
19. CL=0 pF. For CL=30 pF, tSKEW0=0.35 ns.
20. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in
21. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, and so on.)
22. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
23. Specified with outputs loaded with 30 pF for the CY7B99X–2 and –5 devices and 50 pF for the CY7B99X–7 devices. Devices are terminated through 50Ω to
24. tPWH is measured at 2.0V for the CY7B991 and 0.8 VCC for the CY7B992. tPWL is measured at 0.8V for the CY7B991 and 0.2 VCC for the CY7B992.
25. tORISE and tOFALL measured between 0.8V and 2.0V for the CY7B991 or 0.8VCC and 0.2VCC for the CY7B992.
26. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits.
conditions assume signal transition times of 2 ns or less and output loading as shown in the
with 50 pF and terminated with 50Ω to 2.06V (CY7B991) or VCC/2 (CY7B992).
Divide-by-2 or Divide-by-4 mode).
2.06V (CY7B991) or VCC/2 (CY7B992).
This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
Operating Clock
Frequency in MHz
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
Zero Output Matched-Pair Skew
(XQ0, XQ1)
Zero Output Skew (All Outputs)
Output Skew (Rise-Rise, Fall-Fall, Same
Class Outputs)
Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided)
Output Skew (Rise-Rise, Fall-Fall, Different
Class Outputs)
Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted)
Device-to-Device Skew
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation
Output HIGH Time Deviation from 50%
Output LOW Time Deviation from 50%
Output Rise Time
Output Fall Time
PLL Lock Time
Cycle-to-Cycle Output
Jitter
[2, 13]
[16, 17]
[16, 19]
[16, 19]
[26]
Description
[16, 19]
[23, 25]
[16, 19]
[23, 25]
[14, 21]
FS = LOW
FS = MID
FS = HIGH
RMS
Peak-to-Peak
[22]
[16, 18,19]
[14]
[1, 2]
[1, 2]
[1, 2 , 3]
[23, 24]
[23, 24]
[14]
–0.25
–0.65
0.15
0.15
Min
5.0
5.0
15
25
40
CY7B991–2
0.05
0.25
0.25
Typ
0.1
0.3
0.5
0.0
0.0
1.0
1.0
AC Test Loads and Waveforms
[14]
+0.25
+0.65
Max
0.20
0.25
0.75
200
0.5
0.5
0.5
0.9
2.0
1.5
1.2
1.2
0.5
30
50
80
25
See
–0.25
–0.5
Min
5.0
5.0
Table 2
0.5
0.5
15
25
40
CY7B992–2
unless otherwise specified.
0.05
0.25
0.25
Typ
0.1
0.3
0.5
0.0
0.0
2.0
2.0
[14]
+0.25
80
Max
0.20
0.25
0.75
+0.5
200
0.5
0.5
0.5
0.7
3.0
3.0
2.5
2.5
0.5
30
50
25
[15]
CY7B991
CY7B992
Page 9 of 20
MHz
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
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