IDT23S09-1HPGI IDT, Integrated Device Technology Inc, IDT23S09-1HPGI Datasheet
IDT23S09-1HPGI
Specifications of IDT23S09-1HPGI
Related parts for IDT23S09-1HPGI
IDT23S09-1HPGI Summary of contents
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... REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the IDT23S09 enters power down. In this mode, the device will draw less than 12µA for Commercial Temperature range and less than 25µA for Industrial temperature range, and the outputs are tri-stated ...
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... IDT23S09 3.3V ZERO DELAY CLOCK BUFFER PIN CONFIGURATION REF 1 2 CLKA1 CLKA2 GND 6 CLKB1 CLKB2 SOIC/ TSSOP TOP VIEW APPLICATIONS: • SDRAM • Telecom • Datacom • PC Motherboards/Workstations • Critical Path Delay Designs PIN DESCRIPTION Pin Name Pin Number REF 1 (1) ...
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... OUT Measured between 0.8V and 2V Measured between 0.8V and 2V All outputs equally loaded Measured (2) DD Measured PLL bypass mode (IDT23S09 only) (2) DD Measured the CLKOUT pins of devices DD Measured at 66.66MHz, loaded outputs Stable power supply, valid clock presented on REF pin 3 CLKOUT ...
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... Measured between 0.8V and 2V Measured between 0.8V and 2V All outputs equally loaded Measured Measured PLL bypass mode (IDT23S09 only) DD Measured the CLKOUT pins of devices DD Measured between 0.8V and 2V using Test Circuit 2 Measured at 66.66MHz, loaded outputs Stable power supply, valid clock presented on REF pin ...
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... Measured between 0.8V and 2V Measured between 0.8V and 2V All outputs equally loaded Measured Measured PLL bypass mode (IDT23S09 only) DD Measured the CLKOUT pins of devices DD Measured between 0.8V and 2V using Test Circuit 2 Measured at 66.66MHz, loaded outputs Stable power supply, valid clock presented on REF pin ...
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... IDT23S09 3.3V ZERO DELAY CLOCK BUFFER ZERO DELAY AND SKEW CONTROL All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative loading can affect and adjust the input/output delay. The Output Load Difference diagram illustrates the PLL's relative loading with respect to the other outputs that can adjust the Input-Output (I/O) Delay ...
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... IDT23S09 3.3V ZERO DELAY CLOCK BUFFER TEST CIRCUITS V DD 0.1 F OUTPUTS V DD 0.1 F GND GND Test Circuit 1 (all Parameters Except t8) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES CLK OUT 0 LOAD 0.1 F Test Circuit 2 (t8, Output Slew Rate On -1H Devices OUTPUTS GND GND CLK OUT ...
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... IDT23S09 3.3V ZERO DELAY CLOCK BUFFER ORDERING INFORMATION IDT XXXXX XX Device Type Package Process Part / Order Number Shipping Packaging 23S09-1DCG Tubes 23S09-1DCG8 Tape and Reel 23S09-1DCGI Tubes 23S09-1DCGI8 Tape and Reel 23S09-1HDCG Tubes 23S09-1HDCG8 Tape and Reel 23S09-1HDCGI Tubes 23S09-1HDCGI8 Tape and Reel ...