ICS552G-02I IDT, Integrated Device Technology Inc, ICS552G-02I Datasheet - Page 2

• Manufacturer Part Number: ICS552G-02I
• Description: IC MUX/CLOCK BUFFER 16-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generator, Multiplexerr
• Series: ClockBlocks™r

Specifications of ICS552G-02I

• Pll: No
• Input: Clock
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: No/No
• Voltage - Supply: 2.375 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 200MHz
• Number Of Clock Inputs: 2
• Mode Of Operation: Single-Ended
• Output Frequency: 200MHz
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.25V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 552G-02I

IDT™ / ICS™ LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK BUFFER
ICS552-02
LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK BUFFER
Pin Assignment
Pin Descriptions
External Components
A minimum number of external components are required for proper operation. Decoupling capacitors of
0.01 F should be connected between VDD on pin 2 and GND on pin 7, and between VDD on pin 15 and
GND on pin 10, as close to the device as possible. A 33
each clock output if the trace is longer than 1 inch.
To achieve the low output skews that the ICS552-02 is capable of, careful attention must be paid to board
layout. Essentially, all 8 outputs must have identical terminations, identical loads, and identical trace
geometries. If they do not, the output skew will be degraded. For example, using a 30 series termination
on one output (with 33 on the others) will cause at least 15ps of skew.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Number
Pin
GND
VDD
INB
OE
Q0
Q1
Q2
Q3
OE
VDD
Q0
Q1
Q2
Q3
GND
INB
INA
GND
Q4
Q5
Q6
Q7
VDD
SELA
16 Pin TSSOP
1
2
3
4
5
6
7
8
Name
Pin
16
15
14
13
12
11
10
Output
Output
Output
Output
Output
Output
Output
Output
9
Power
Power
Power
Power
Type
Input
Input
Input
Input
Pin
SELA
VDD
Q7
Q6
Q5
Q4
GND
INA
Output Enable. Tri-states outputs when low. Internal pull-up resistor.
Connect to +2.5V, +3.3V or +5.0V. Must be the same as pin 15.
Clock Output 0
Clock Output 1
Clock Output 2
Clock Output 3
Connect to ground.
Clock Input B. 5V tolerant input.
Clock Input A. 5V tolerant input.
Connect to ground.
Clock Output 4
Clock Output 5
Clock Output 6
Clock Output 7
Connect to + 2.5V, +3.3V or +5.0V. Must be the same as pin 2.
Selects either INA or INB. Internal pull-up resistor.
2
Input Source Select
series terminating resistor should be used on
Pin Description
SELA
0
1
Input
CLOCK MUX AND BUFFER
INB
INA
ICS552-02
REV L 051310