MK2771-16R IDT, Integrated Device Technology Inc, MK2771-16R Datasheet - Page 3

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MK2771-16R

Manufacturer Part Number
MK2771-16R
Description
IC CLK SRC VCXO/SET-TOP 28-QSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Synthesizer, VCXOr
Datasheet

Specifications of MK2771-16R

Pll
Yes with Bypass
Input
Crystal
Output
CMOS
Number Of Circuits
1
Ratio - Input:output
2:8
Differential - Input:output
No/No
Frequency - Max
50MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
28-QSOP
Frequency-max
50MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Pin Descriptions
IDT™ VCXO AND SET-TOP CLOCK SOURCE
MK2771-16
VCXO AND SET-TOP CLOCK SOURCE
18, 23, 25
19, 20, 24
3, 10, 11
Number
5, 8, 22
Pin
12
13
14
15
16
17
21
26
27
28
1
2
4
6
7
9
CCLK2
CCLK1
VDDIO
13.5M
Name
VDD5
PCLK
ACLK
GND
GND
CS1
27M
CS0
PS0
PS1
AS2
AS0
AS1
Pin
VIN
X2
X1
Tri-level Input Processor Clock Select 1. Selects PCLK frequency. See table
Pin Type
Output
Output
Output
Output
Output
Output
Power
Power
Power
Power
Input
Input
Input
Input
Input
Input
Input
XO
XI
Processor clock select 0. Selects PCLK frequency. See table
above. Internal pull-up resistor.
Crystal connection. Connect to a 13.5 MHz fundamental mode
pullable crystal.
Connect to ground.
Crystal connection. Connect to a 13.5 MHz fundamental mode
pullable crystal.
Connect to +5 V.
Voltage input to VCXO. Zero to 3 V signal which controls the
frequency of the VCXO.
Connect to +3.3 V or +5 V. Amplitude of inputs and outputs will
match this.
Communications clock select pin 1. Selects CCLK 1 and 2 per
table above. Internal pull-up.
Processor clock output. Determined by status of PS1, PS0.
Communications clock output 2 determined by status of CS1,
CS0 per table above.
Audio clock output. Determined by status of AS2:0 per table
above.
13.5 MHz VCXO clock output.
above. Self-biased to M.
Communications clock output 1 determined by status of CS1,
CS0 per table above.
27 MHz VCXO clock output.
Connect to ground.
Audio clock select 2. Selects ACLK on pin 14. See table above.
Internal pull-up resistor.
Communications clock select pin 0. Selects CCLK 1 and 2 per
table above. Internal pull-up.
Audio clock select 0. Selects ACLK on pin 14. See table above.
Internal pull-up resistor.
Audio clock select 1. Selects ACLK on pin 14. See table above.
Internal pull-up resistor.
3
Pin Description
VCXO AND SYNTHESIZER
MK2771-16
REV G 051310

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