MK1574-01ASI IDT, Integrated Device Technology Inc, MK1574-01ASI Datasheet - Page 7

• Manufacturer Part Number: MK1574-01ASI
• Description: IC PLL FRAME RATE COMM 16-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock/Frequency Synthesizerr

Specifications of MK1574-01ASI

• Pll: Yes
• Input: Clock
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: No/No
• Divider/multiplier: No/Yes
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Frequency-max: -

Loop Bandwidth and Loop Filter Component Selection
IDT™ / ICS™ FRAME RATE COMMUNICATIONS PLL
MK1574-01A/B
FRAME RATE COMMUNICATIONS PLL
The series-connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic
characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore a high quality
ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic capacitor. The series
connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic characteristics of
the phase-locked loop. The capacitor must have very low leakage, therefore a high quality ceramic capacitor is
recommended. DO NOT use any type of polarized or electrolytic capacitor. Ceramic capacitors should have C0G or
NP0 dielectric. Avoid high-K dielectrics like Z5U and X7R; these and other ceramics which have piezoelectric
properties allow mechanical vibration in the system to increase the output jitter because the mechanical energy is
converted directly to voltage noise on the VCO input.
The values of the RC network determine the bandwidth of the PLL. The values of the loop filter components are
calculated using the constants K1 and K2 from the Loop Filter Constants table (page 7). The loop bandwidth is set
by the capacitor C and the constant K1 using the formula:
BW (Hz) =
The loop damping is set by the resistor R, the capacitor C, and the constant K2 using the formula::
For example, to design the loop filter whewn generating 8.192 MHz from 8 kHz:
1. From the Output Clock Decoding table (page 2), the address is E. The Loop Filter Constants table (page 7)
2. A good value for the loop bandwidth is 1/20 the input frequency; where 8 kHz/20 = 400 Hz. Using equation 1,
Therefore,
3. A good value for the damping factor
R =
C =
R =
400 =
shows the constants K1 = 0.0516 and K2 = 6.2.
(
0.707 * 6.2
C
* K2
0.0516
16E-9
K1
K1
400
C
C
K1
C
) 2
= 34.7 k (36 k nearest standard value)
= 16.6 nF (16 nF nearest standard value
Equation 1
Equation 2;
is 0.707. From equation 2,
(zeta) is the damping factor
7
MK1574-01A/B
CLOCK SYNTHESIZER
REV D 051310