SI5338C-A-GM Silicon Laboratories Inc, SI5338C-A-GM Datasheet - Page 21

• Manufacturer Part Number: SI5338C-A-GM
• Description: IC CLK GEN QUAD 200MHZ 24-QFN
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Generatorr

Specifications of SI5338C-A-GM

• Pll: Yes
• Input: CML, HCSL, HSCL, LVDS, LVPECL, Crystal
• Output: CMOS, HCSL. HSTL. LVDS. LVPECL. SSTL
• Number Of Circuits: 1
• Ratio - Input:output: 3:4
• Differential - Input:output: Yes/Yes
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 1.71 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-QFN
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1747 - KIT PROG FIELD SI5338/4/0336-1556 - BOARD EVALUATION SI5338
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1555-5

Input clocks are
validated with the
LOS alarms. See
Register 218 to
determine which LOS
should be monitored
Use ClockBuilder
Desktop v3.0 or later
PLL is locked when
PLL_LOL, SYS_CAL, and
all other alarms are
cleared
Register
Map
Figure 9. I
accounting for the write-allowed mask
Set FCAL_OVRD_EN = 0; reg49[7]
Set FCAL_OVRD_EN = 1; reg49[7]
Set SOFT_RESET = 1; reg246[1]
2
Write new configuration to device
C Programming Procedure
Set OEB_ALL = 1; reg230[4]
Set OEB_ALL = 0; reg230[4]
Set PLL to use FCAL values
Set DIS_LOL = 1; reg241[7]
Set DIS_LOL = 0; reg241[7]
Validate input clock status
Configure PLL for locking
Confirm PLL lock status
Initiate Locking of PLL
Copy FCAL values to
Is input clock valid?
Set reg 241 = 0x65
Rev. 1.0
Disable Outputs
Enable Outputs
active registers
Is PLL locked?
(See AN411)
Restart LOL
Pause LOL
Wait 25 ms
YES
YES
Copy registers as follows:
237[1:0] to 47[1:0]
236[7:0] to 46[7:0]
235[7:0] to 45[7:0]
Set 47[7:2] = 000101b
NO
NO
Si5338
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