MC74HC4046AFELG ON Semiconductor, MC74HC4046AFELG Datasheet - Page 9

• Manufacturer Part Number: MC74HC4046AFELG
• Description: IC PHASE LOCKED LOOP 16SOEIAJ
• Manufacturer: ON Semiconductor
• Series: 74HCr
• Type: Phase Lock Loop (PLL)r

Specifications of MC74HC4046AFELG

• Pll: Yes
• Input: CMOS
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:4
• Frequency - Max: 13MHz
• Divider/multiplier: No/No
• Voltage - Supply: 3 V ~ 6 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (5.3mm Width), 16-SO, 16-SOEIIJ
• Frequency-max: 13MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC74HC4046AFELGOS; MC74HC4046AFELGOS; MC74HC4046AFELGOSTR

Phase Comparator 2
four flip−flops and some gating logic, a three state output
and a phase pulse output as shown in Figure 6. This
comparator acts only on the positive edges of the input
signals and is independent of duty cycle.
PLL into lock with 0 phase difference between the VCO
output and the signal input positive waveform edges. Figure
8 shows some typical loop waveforms. First assume that
SIG
frequency must be increased to bring its leading edge into
proper phase alignment. Thus the phase detector 2 output is
set high. This will cause the loop filter to charge up the VCO
input, increasing the VCO frequency. Once the leading edge
of the COMP
holding the VCO input at the loop filter voltage. If the VCO
still lags the SIG
up the VCO input for the time between the leading edges of
both waveforms.
the VCO is seen; the output of the phase comparator goes
low. This discharges the loop filter until the leading edge of
the SIG
again. This has the effect of slowing down the VCO to again
make the rising edges of both waveforms coincidental.
either slower or faster than the SIG
the phase detector will see more SIG
the output of the phase comparator will be high a majority
of the time, raising the VCO’s frequency. Conversely, if the
VCO is running faster than the SIG
detector will be low most of the time and the VCO’s output
frequency will be decreased.
phase comparator 2 will be disabled except for minor
corrections at the leading edge of the waveforms. When PC
is TRI−STATED, the PCP output is high. This output can be
used to determine when the PLL is in the locked condition.
the entire VCO frequency range there is no phase difference
between the COMP
PLL is the same as the capture range. Minimal power was
consumed in the loop filter since in lock the detector output
is a high impedance. When no SIG
will see only VCO leading edges, so the comparator output
will stay low, forcing the VCO to f
the PLL to unlock. If a noise pulse is seen on the SIG
comparator treats it as another positive edge of the SIG
This detector is a digital memory network. It consists of
Phase comparator 2 operates in such a way as to force the
If the VCO leads the SIG
When the PLL is out of lock, the VCO will be running
As one can see, when the PLL is locked, the output of
This detector has several interesting characteristics. Over
Phase comparator 2 is more susceptible to noise, causing
IN
is leading the COMP
IN
is detected at which time the output disables itself
IN
IN
is detected, the output goes TRI−STATE
then the phase detector will again charge
IN
and the SIG
IN
IN
then when the leading edge of
. This means that the VCO’s
IN
IN
IN
min
. The lock range of the
. If it is running slower
is present, the detector
IN
IN
.
rising edges and so
, the output of the
http://onsemi.com
MC74HC4046A
IN
, the
IN
2
9
and will cause the output to go high until the VCO leading
edge is seen, potentially for an entire SIG
would cause the VCO to speed up during that time. When
using PC
disturbed for only the short duration of the noise spike and
would cause less upset.
Phase Comparator 3
detector using an RS flip−flop as shown in Figure 7. When
the PLL is using this comparator, the loop is controlled by
positive signal transitions and the duty factors of SIG
COMP
characteristics to the edge sensitive comparator. To see how
this detector works, assume input pulses are applied to the
SIG
SIG
loop filter and cause the VCO to speed up, bringing the
comparator into phase with the SIG
between SIG
180° at f
but consequently has more ripple in the signal to the VCO.
When no SIG
opposed to f
comparators should be compared to the requirements of the
system design and the appropriate one should be used.
COMP
PC3
PCP
COMP
PC2
This is a positive edge−triggered sequential phase
The operating characteristics of all three phase
VCO
VCO
SIG
SIG
IN
IN
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
leads the COMP
Figure 9. Typical Waveforms for PLL Using
Figure 10. Typical Waveform for PLL Using
and COMP
IN
o
. The voltage swing for PC
1
, the output of that phase detector would be
are not important. It has some similar
min
IN
IN
and COMP
when PC
is present the VCO will be forced to f
Phase Comparator 2
Phase Comparator 3
IN
’s as shown in Figure 10. When the
IN
, the flop is set. This will charge the
2
HIGH IMPEDANCE OFF−STATE
is used.
IN
varies from 0° to 360° and is
3
is greater than for PC
IN
. The phase angle
IN
period. This
IN
max
and
V
GND
VCC
GND
CC
as
2