DS1085Z-25+ Maxim Integrated Products, DS1085Z-25+ Datasheet - Page 19

• Manufacturer Part Number: DS1085Z-25+
• Description: IC ECONOSCILLATOR SYNTH 8-SOIC
• Manufacturer: Maxim Integrated Products
• Series: EconOscillator™r
• Type: Frequency Synthesizerr

Specifications of DS1085Z-25+

• Pll: No
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 133MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 133MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9) This indicates the time taken between power-up and the outputs becoming active. An on-chip delay is
10) Output voltage swings can be impaired at high frequencies combined with high-output loading.
11) After this period, the first clock pulse is generated.
12) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the
13) The maximum t
14) A fast-mode device can be used in a standard mode system, but the requirement t
15) C
16) EEPROM write begins after a STOP condition occurs.
17) Typical frequency shift due to aging is ±0.5%. Aging stressing includes Level 1 moisture reflow
Figure 5. MASTER FREQUENCY TEMPERATURE VARIATION
intentionally introduced to allow the oscillator to stabilize. t
clock cycles and hence depends on the programmed clock frequency.
V
SCL signal.
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL
signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line at least t
released.
preconditioning (24hr +125°C bake, 168hr 85°C/85%RH moisture soak, and 3 solder reflow passes
+240 +0/-5°C peak) followed by 1000hr max V
55°C to +125°C, 96hr 130°C/85%RH/5.5V HAST and 168hr 121°C/2 ATM Steam/Unbiased
Autoclave.
B
IH MIN
—total capacitance of one bus line in picofarads; timing referenced to 0.9V
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
HD:DAT
need only be met if the device does not stretch the LOW period (t
R MAX
-0 .5 0
-1 .0 0
-1 .5 0
-2 .0 0
2 .0 0
1 .5 0
1 .0 0
0 .5 0
0 .0 0
6 6 .0 0
M A S T E R F R E Q U E N C Y T E M P E R A T U R E
M A S TE R O S C IL L A TO R F R E Q U E N C Y (M H z )
+ t
SU:DAT
8 2 .7 5
V A R IA T IO N
19 of 21
= 1000ns + 250ns = 1250ns before the SCL line is
CC
9 9 .5 0
biased 125°C HTOL, 1000 temperature cycles at -
1 1 6 . 2 5
stab
1 3 3 . 0 0
is equivalent to approximately 8000
CC
and 0.1V
SU:DAT
> 250ns must
CC
LOW
.
) of the