MC100EP40DTR2 ON Semiconductor, MC100EP40DTR2 Datasheet

MC100EP40DTR2

Manufacturer Part Number

MC100EP40DTR2

Description

IC DETECT PHASE FREQ ECL 20TSSOP

Manufacturer

ON Semiconductor

Series

100EPr

Type

Phase Frequency Detectorr

Datasheet

1.MC100EP40DTR2.pdf (9 pages)

Specifications of MC100EP40DTR2

Pll

Yes

Input

CML, NECL, PECL

Output

ECL

Number Of Circuits

Ratio - Input:output

1:2

Differential - Input:output

Yes/Yes

Frequency - Max

2GHz

Divider/multiplier

No/No

Voltage - Supply

±3 V ~ 5.5 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

20-TSSOP

Frequency-max

2GHz

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Other names

MC100EP40DTR2OSTR

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Allchip Electronic(HK) Limited

Part Number:

MC100EP40DTR2

Manufacturer:

Quantity:

14 644

Current page: 1 of 9
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MC100EP40

3.3V / 5V ECL Differential

Phase-Frequency Detector

Description

intended for phase−locked loop applications which require a minimum

amount of phase and frequency difference at lock. Advanced design

significantly reduces the dead zone of the detector. For proper

operation, the input edge rate of the R and V inputs should be less than

5 ns. The device is designed to work with a 3.3 V / 5 V power supply.

frequency and/or phase the differential UP (U) and DOWN (D)

outputs will provide pulse streams which when subtracted and

integrated provide an error voltage for control of a VCO.

phase difference, the Phase Lock Detect pin will indicate lock by a

high state (V

internal termination network for 50 W line impedance environment

shown in Figure 2. An external sinking supply of V

on V

For more information on termination of logic devices, see AND8020.

this device only. For single-ended input conditions, the unused

differential input is connected to V

and V

to 0.5 mA. When not used, V

AND8040.

Signal conditions to prevent instability.

Features

•

November, 2008 − Rev. 12

TFB

The MC100EP40 is a three−state phase−frequency detector

When Reference (R) and Feedback (FB) inputs are unequal in

When Reference (R) and Feedback (FB) inputs are 80 ps or less in

The V

For more information on Phase Lock Loop operation, refer to

Special considerations are required for differential inputs under No

with V

Maximum Frequency > 2 GHz Typical

Fully Differential

Advanced High Band Output Swing of 400 mV

Theoretical Gain = 1.11

The 100 Series Contains Temperature Compensation

PECL Mode Operating Range: V

NECL Mode Operating Range: V

50 W Internal Termination Resistor

These are Pb−Free Devices

rise

may also rebias AC coupled inputs. When used, decouple V

and V

97 ps Typical, F

pin(s). If you short the two differential pins V

via a 0.01 mF capacitor and limit current sourcing or sinking

TFB

pin, an internally generated voltage supply, is available to

= −3.0 V to −5.5 V

= 0 V

) together, you provide a 100 W termination resistance.

). The V

fall

70 ps Typical

should be left open.

, V

as a switching reference voltage.

= 3.0 V to 5.5 V

= 0 V

, V

TFB

, V

TFB

−2 V is required

) pins offer an

and V

(or

See detailed ordering and shipping information in the package

dimensions section on page 7 of this data sheet.

*For additional marking information, refer to

(Note: Microdot may be in either location)

Application Note AND8002/D.

CASE 948E

ORDERING INFORMATION

DT SUFFIX

TSSOP−20

http://onsemi.com

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

Publication Order Number:

DIAGRAM*

MARKING

ALYW G

MC100EP40/D

EP40

100

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MC100EP40DTR2 Summary of contents

Page 1

MC100EP40 3.3V / 5V ECL Differential Phase-Frequency Detector Description The MC100EP40 is a three−state phase−frequency detector intended for phase−locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design significantly reduces the dead zone of ...

Page 2

V PLD VTFB VTFB Warning: All V and V pins must be externally connected ...

Page 3

Table 2. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see ...

Page 4

Table 4. 100EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 5

Table 6. 100EP DC CHARACTERISTICS, NECL Symbol Characteristic I Power Supply Current (Note 10 Output HIGH Voltage (Note 11 Output LOW Voltage (Note 11 Input HIGH Voltage (Single−Ended ...

Page 6

V 400 350 300 (JITTER) Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï 250 Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï 1.0 1.5 ...

Page 7

... ORDERING INFORMATION Device MC100EP40DT MC100EP40DTG MC100EP40DTR2 MC100EP40DTR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D AN1504/D ...

Page 8

... −V− 0.100 (0.004) −T− SEATING PLANE 16X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−20 CASE 948E−02 ISSUE Í Í Í Í ...

Page 9

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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