CY26049ZXI-36T Cypress Semiconductor Corp, CY26049ZXI-36T Datasheet

CY26049ZXI-36T

Manufacturer Part Number

CY26049ZXI-36T

Description

IC CLOCK GEN 3.3V 16-TSSOP

Manufacturer

Cypress Semiconductor Corp

Type

Clock/Frequency Synthesizer, Clock Generator, Fanout Distribution, Jitter Attenuatorr

Series

Failsafe™, PacketClock™r

Datasheet

1.CY26049ZXC-36.pdf (7 pages)

Specifications of CY26049ZXI-36T

Number Of Circuits

Package / Case

16-TSSOP

Pll

Yes with Bypass

Input

Clock

Output

Clock

Ratio - Input:output

1:3

Differential - Input:output

No/No

Frequency - Max

155MHz

Divider/multiplier

Yes/No

Voltage - Supply

3.15 V ~ 3.45 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Frequency-max

155MHz

Maximum Input Frequency

60 MHz

Minimum Input Frequency

10 MHz, 0.008 MHz

Output Frequency Range

0.008 MHz to 155.52 MHz

Supply Voltage (max)

3.45 V

Supply Voltage (min)

3.15 V

Maximum Operating Temperature

+ 85 C

Minimum Operating Temperature

- 40 C

Mounting Style

SMD/SMT

Operating Supply Voltage

3.3 V

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

For Use With

428-1918 - KIT DEV FTG PROGRAMMING KIT

Lead Free Status / RoHS Status

Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

H&T Electronics

Part Number:

CY26049ZXI-36T

Quantity:

2 600

Current page: 1 of 7
Download datasheet (145Kb)

Cypress Semiconductor Corporation

Document #: 38-07415 Rev. *C

Features

Benefits

• Fully integrated phase-locked loop (PLL)

• FailSafe output

• PLL driven by a crystal oscillator that is phase aligned

• Output frequencies selectable and/or programmed to

• Low-jitter, high-accuracy outputs

• Commercial and Industrial operation

• 3.3V ± 5% operation

• 16-lead TSSOP

• Integrated high-performance PLL tailored for telecom-

Logic Block Diagram

Pin Configuration

with external reference

standard communication frequencies

munications frequency synthesis eliminates the need

for external loop filter components

frequency select

Input reference

(typical 8 kHz)

FailSafe™ PacketClock™ Global Communications

FS[3:0]

ICLK

•

CLK/2 7

FAILSAFE

High=ICLK detected

SAFE

ICLK 1

CONTROL

VDD 5

VSS 6

FS1 3

FS2 4

XIN 8

8K 2

3901 North First Street

16-pin TSSOP

CY26049-36

Top View

external pullable crystal

XIN

CONTROLLED

OSCILLATOR

(18.432 MHz)

CRYSTAL

DIGITAL

• When reference is in range, SAFE pin is driven high.

• When reference is off, DCXO maintains clock outputs.

• DCXO maintains continuous operation should the input

• Glitch-free transition simplifies system design

• Selectable output clock rates include T1/DS1, E1,

• Works with commonly available, low-cost 18.432-MHz

• Zero-ppm error for all output frequencies

• Performance guaranteed for applications that require

• Compatible across industry standard design platforms

• Industry standard package with 6.4 x 5.0 mm

16 NC

15 CLK

14 FS0

13 FS3

12 VDD

11 VSS

10 SAFE

9 XOUT

XOUT

SAFE pin is low.

reference clock fail

T3/DS3, E3, and OC-3.

crystal

an extended temperature range

and a height profile of just 1.1 mm.

LOCKED

•

PHASE

LOOP

San Jose

DIVIDERS

OUTPUT

CA 95134

Clock Generator

CLK

CLK/2

Revised July 16, 2004

•

CY26049-36

408-943-2600

footprint

Related parts for CY26049ZXI-36T

CY26049ZXI-36T Summary of contents

Page 1

... ICLK FS[3:0] frequency select Pin Configuration Cypress Semiconductor Corporation Document #: 38-07415 Rev. *C • When reference is in range, SAFE pin is driven high. • When reference is off, DCXO maintains clock outputs. SAFE pin is low. • DCXO maintains continuous operation should the input reference clock fail • ...

Page 2

Pin Definitions Pin Name Pin Number ICLK 1 Reference Input Clock; 8 kHz MHz Clock Output; 8 kHz or high impedance in buffer mode. FS1 3 Frequency Select 1; Determines CLK outputs per Table ...

Page 3

Frequency Select Tables Table 1. CY26049-36 Frequency Select–Output Decoding Table–External Mode (MHz except as noted) ICLK FS3 FS2 8 kHz kHz kHz kHz kHz kHz ...

Page 4

Absolute Maximum Conditions Supply Voltage (V ) ........................................–0.5 to +7. Input Voltage........................................ –0. Storage Temperature (Non-Condensing) .... –55°C to +125°C Junction Temperature ................................ –40°C to +125°C Recommended Pullable Crystal Specifications Parameter Description F Nominal crystal frequency ...

Page 5

DC Electrical Specifications Parameter Description I Output High Current OH I Output Low Current OL V Input High Voltage IH V Input High Voltage IL I Input High Current IH I Input Low Current IL C Input Capacitance IN I ...

Page 6

... LOAD VDD 0.1uF CLK/2 C LOAD Ordering Information Ordering Code CY26049ZC-36 CY26049ZC-36T CY26049ZI-36 CY26049ZI-36T Lead Free CY26049ZXC-36 CY26049ZXC-36T CY26049ZXI-36 CY26049ZXI-36T Package Diagram 1 4.30[0.169] 4.50[0.177] 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 0.05[0.002] 0.85[0.033] 0.15[0.006] 0.95[0.037] 4.90[0.193] 5.10[0.200] FailSafe and PacketClock are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders ...

Page 7

Document History Page Document Title: CY26049-36 FailSafe™ PacketClock™ Global Communications Clock Generator Document Number: 38-07415 Orig. of REV. ECN NO. Issue Date Change ** 114749 08/08/02 *A 120067 01/06/03 *B 128000 07/15/03 *C 244412 See ECN Document #: 38-07415 Rev. ...

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