CY28409ZXCT Cypress Semiconductor Corp, CY28409ZXCT Datasheet
CY28409ZXCT
Specifications of CY28409ZXCT
Related parts for CY28409ZXCT
CY28409ZXCT Summary of contents
Page 1
... SDATA I C SCLK Logic Note: 1. Signals marked with [*] and [**] have internal pull-up and pull-down resistors, respectively. Cypress Semiconductor Corporation Document #: 38-07445 Rev. *D Clock Synthesizer with Differential SRC and • Three differential CPU clock pairs • One differential SRC clock 2 • support with readback capabilities • ...
Page 2
Pin Description Pin No. Name Type 1, 2 REF(0: Reference Clock. 3.3V 14.318-MHz clock output. 4 XIN I 5 XOUT O, SE Crystal Connection. Connection for an external 14.318-MHz crystal output. 41,44,47 CPUT(0:2) O, DIF CPU Clock Output. ...
Page 3
Table 1. Frequency Select Table (FS_A, FS_B) FS_A FS_B CPU 0 0 100 MHz 100/200 MHz 0 MID REF 200 MHz 100/200 MHz 1 0 133 MHz 100/200 MHz 1 MID Hi-Z Table 2. Frequency Select Table (FS_A, ...
Page 4
Table 4. Block Read and Block Write Protocol (continued) Block Write Protocol Bit Description 20:27 Byte Count – 8 bits 28 Acknowledge from slave 29:36 Data byte 1 – 8 bits 37 Acknowledge from slave 38:45 Data byte 2 – ...
Page 5
Byte 0:Control Register 0 (continued) Bit @Pup 3 Externally PCI_STP# Selected 2 Externally CPU_STP# Selected 1 Externally FS_B Selected 0 Externally FS_A Selected Byte 1: Control Register 1 Bit @Pup 7 0 SRCT, SRCC 6 1 SRCT, SRCC 5 1 ...
Page 6
Byte 3: Control Register 3 (continued) Bit @Pup 5 1 PCI5 4 1 PCI4 3 1 PCI3 2 1 PCI2 1 1 PCI1 0 1 PCI0 Byte 4: Control Register 4 Bit @Pup 7 0 USB_48 6 1 USB_48 5 ...
Page 7
Byte 6: Control Register 6 Bit @Pup 7 0 Reserved 6 0 Reserved 5 0 CPUC0, CPUT0 CPUC1, CPUT1 CPUC2, CPUT2 4 0 SRCT, SRCC 3 0 Reserved 2 0 PCIF PCI 3V66 SRCT,SRCC CPUT_ITP,CPUC_ITP 1 1 REF_1 0 1 ...
Page 8
Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with ...
Page 9
PD# Deassertion The power-up latency between PD# rising to a valid logic ‘1’ level and the starting of all clocks is less than 1.8 ms. CPU_STP# Assertion The CPU_STP# signal is an active LOW input used for synchronous stopping and ...
Page 10
PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ...
Page 11
FS_A, FS_B VTT_PWRGD# PWRGD_VRM 0.2-0.3 ms VDD Clock Gen Clock State State 0 Off Clock Outputs Off Clock VCO VDDA = 2.0V S0 Power Off Figure 10. Clock Generator Power-up/Run State Diagram Document #: 38-07445 Rev. *D Wait for Sample ...
Page 12
Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DD_A V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J Ø Dissipation, Junction to Case JC Ø Dissipation, ...
Page 13
AC Electrical Specifications Parameter Description CPU at 0.7V T CPUT and CPUC Duty Cycle DC T 100-MHz CPUT and CPUC Period PERIOD T 133-MHz CPUT and CPUC Period PERIOD T 200-MHz CPUT and CPUC Period PERIOD T Any CPUT/C to ...
Page 14
AC Electrical Specifications Parameter Description PCIF and PCI rise and fall times Any PCI clock to Any PCI clock Skew Measurement at 1.5V SKEW T PCIF and PCI Cycle to Cycle Jitter CCJ DOT ...
Page 15
... SSOP – Tape and Reel CY28409ZC 56-pin TSSOP CY28409ZCT 56-pin TSSOP – Tape and Reel PB-Free CY28409OXC 56-pin SSOP CY28409OCXT 56-pin SSOP – Tape and Reel CY28409ZXC 56-pin TSSOP CY28409ZXCT 56-pin TSSOP – Tape and Reel Document #: 38-07445 Rev Ω Ω Ω Ω ...
Page 16
... Document #: 38-07445 Rev. *D © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...
Page 17
Document History Page Document Title: CY28409 Clock Synthesizer with Differential SRC and CPU Outputs Document Number: 38-07445 REV. ECN NO. Issue Date ** 121414 12/04/02 *A 124795 07/07/03 *B 128864 08/29/03 *C 340360 See ECN *D 417655 See ECN Document ...