CY28441ZXC Cypress Semiconductor Corp, CY28441ZXC Datasheet
CY28441ZXC
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CY28441ZXC Summary of contents
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... IREF PD PLL2 2 SDATA I C Logic SCLK Cypress Semiconductor Corporation Document #: 38-07679 Rev. ** Clock Generator for Intel • 33-MHz PCI clock • Low-voltage frequency select input 2 • support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • ...
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Pin Description Pin No. Name 33, 32 CLKREQA#, CLKREQB#, 54 CPU_STP# 44, 43, 41, 40 CPUT/C O, DIF Differential CPU clock outputs. 36, 35 CPUT2_ITP/SRCT7, O, DIF Selectable differential CPU or SRC clock output. CPUC2_ITP/SRCC7 14, 15 DOT96T, DOT96C O, ...
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Pin Description Pin No. Name 50 XIN 49 XOUT O, SE 14.318-MHz crystal output. Frequency Select Pins (FS_A, FS_B and FS_C) Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C inputs prior to ...
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Table 3. Block Read and Block Write Protocol (continued) Block Write Protocol Bit Description 27:20 Byte Count – 8 bits 28 Acknowledge from slave 36:29 Data byte 1 – 8 bits 37 Acknowledge from slave 45:38 Data byte 2 – ...
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Byte 0:Control Register 0 (continued) Bit @Pup Name 2 1 SRC[T/C SRC[T/C SRC[T/C]0 Byte 1: Control Register 1 Bit @Pup Name 7 1 PCIF0 6 1 DOT_96T USB_48 4 1 REF 3 0 Reserved ...
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Byte 3: Control Register 3 (continued) Bit @Pup Name 4 0 SRC4 3 0 SRC3 2 0 SRC2 1 0 SRC1 0 0 SRC0 Byte 4: Control Register 4 Bit @Pup Name 7 0 Reserved 6 0 DOT96T ...
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Byte 6: Control Register 6 (continued) Bit @Pup Name Reserved 4 1 REF 3 1 PCIF, SRC, PCI 2 Externally CPUT/C selected 1 Externally CPUT/C selected 0 Externally CPUT/C selected Byte 7: Vendor ID Bit @Pup ...
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Table 5. Crystal Recommendations Frequency Cut Loading Load Cap (Fund) 14.31818 MHz AT Parallel Crystal Recommendations The CY28441 requires a Parallel Resonance Crystal. Substi- tuting a series resonance crystal will cause the CY28441 to operate at the wrong frequency and ...
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CLKREQ#X SRCT(free running) SRCC(free running) SRCT(stoppable) SRCT(stoppable) Figure 3. CLK_REQ#[A:B] Deassertion/Assertion Waveform CLK_REQ[A:B]# Assertion (CLKREQ# -> LOW) All differential outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the assertion ...
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PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33MHz REF Figure 5. Power-down Deassertion Timing Waveform PD Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of ...
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CPU_STP# Deassertion The deassertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no CPU_STP# CPUT CPUC CPUT Internal CPUC Internal CPU_STOP# PD CPUT(Free Running ...
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PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ...
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FS_A, FS_B,FS_C VTT_PW RGD# PW RGD_VRM 0.2-0.3mS VDD Clock Gen Clock State State 0 Off Clock Outputs Off Clock VCO VDD_A = 2.0V S0 Power Off Figure 13. Clock Generator Power-up/Run State Diagram Document #: 38-07679 Rev ait ...
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Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DD_A V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J Ø Dissipation, Junction to Case JC Ø Dissipation, ...
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AC Electrical Specifications Parameter Description Crystal T XIN Duty Cycle DC T XIN Period PERIOD XIN Rise and Fall Times XIN Cycle to Cycle Jitter CCJ L Long-term Accuracy ACC CPU at 0.7V T ...
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AC Electrical Specifications (continued) Parameter Description T Any SRCT/C to SRCT/C Clock Skew SKEW T SRCT/C Cycle to Cycle Jitter CCJ L SRCT/C Long Term Accuracy ACC SRCT and SRCC Rise and Fall Times ...
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AC Electrical Specifications (continued) Parameter Description Long Term Jitter @ 10 µs T LTJ USB T Duty Cycle DC T Period PERIOD T Absolute Period PERIODAbs T USB High Time HIGH T USB Low Time LOW Rise ...
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Test and Measurement Set-up The following diagram shows the test load configurations for the single-ended USB, and REF output signals 6 0 Ω Ω Ω Ω ...
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... Figure 16. Single-ended Output Signals (for AC Parameters Measurement) Ordering Information Part Number Lead-free CY28441ZXC 56-pin TSSOP CY28441ZXCT 56-pin TSSOP – Tape and Reel Package Diagrams 56-Lead Thin Shrunk Small Outline Package, Type mm) Z56 0.249[0.009 13.894[0.547] 14.097[0.555] 0.851[0.033] 0.500[0.020] 0.950[0.037] BSC Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders ...
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Document History Page Document Title: CY28441 Clock Generator for Intel Document Number: 38-07679 REV. ECN NO. Issue Date ** 237792 See ECN RGL/SDR New Data Sheet Document #: 38-07679 Rev. ** Alviso Chipset Orig. of Change Description of Change ...