CY28RS480ZXC Cypress Semiconductor Corp, CY28RS480ZXC Datasheet

IC CLOCK GENERATOR 56-TSSOP

CY28RS480ZXC

Manufacturer Part Number
CY28RS480ZXC
Description
IC CLOCK GENERATOR 56-TSSOP
Manufacturer
Cypress Semiconductor Corp
Type
Clock Generatorr
Datasheet

Specifications of CY28RS480ZXC

Frequency - Max
200MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-TSSOP II
Frequency-max
200MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Output
-
Input
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY28RS480ZXC
Manufacturer:
MAXIM
Quantity:
160
Part Number:
CY28RS480ZXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
CLKREQ[0:1]#
Cypress Semiconductor Corporation
Document #: 38-07638 Rev. *C
Features
• Supports AMD
• 200-MHz differential CPU clock pairs
• 100-MHz differential SRC clocks
• 48-MHz USB clock
• 33-MHz PCI clock
• 66-MHz HyperTransport clock
Block Diagram
CPU_STP#
SDATA
XOUT
SCLK
IREF
XIN
PD
PLL1
PLL2
Logic
XTAL
OSC
I
2
C
CPU
Network
Divider
PLL Ref Freq
Clock Generator for ATI
3901 North First Street
VDD_REF
REF[0:2]
VDD_CPU
VDD_SRC
VDD_PCI
VDD_48 MHz
USB_48
CPUT[0:1], CPUC[0:1],
SRCT[0:5],SRCC[0:5]
VDD_SRCS
SRCST[0:1],SRCSC[0:1]
PCI
VDD_HTT
HTT66
• I
• Ideal Lexmark Spread Spectrum profile for maximum
• 3.3V power supply
• 56-pin SSOP and TSSOP packages
CPU
electromagnetic interference (EMI) reduction
x2
2
CLKREQ#0
CLKREQ#1
C support with readback capabilities
Pin Configuration
VDD_SRC
VDD_SRC
VSS_SRC
VSS_SRC
VSS_SRC
SRCSC1
SRCST1
VDD_48
USB_48
VSS_48
SRCC5
SRCC4
SRCC3
SRCC2
SRCC1
SRCT5
SRCT4
SRCT3
SRCT2
SRCT1
SDATA
XOUT
SCLK
XIN
SRC
NC
NC
x8
San Jose
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 SSOP/TSSOP
HTT66
x1
,
CA 95134
Revised February 21, 2005
RS480 Chipset
PCI
x1
32
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
31
30
29
CY28RS480
VDD_REF
VSS_REF
REF0
REF1
REF2
VDD_PCI
PCI0
VSS_PCI
VDD_HTT
HTT66
VSS_HTT
CPUT0
CPUC0
VDD_CPU
VSS_CPU
CPUT1
CPUC1
VDDA
VSSA
IREF
VSS_SRC1
VDD_SRC1
SRCT0
SRCC0
VDD_SRCS
VSS_SRCS
SRCST0
SRCSC0
REF
x 3
408-943-2600
USB_48
x 1
[+] Feedback

Related parts for CY28RS480ZXC

CY28RS480ZXC Summary of contents

Page 1

... IREF PD PLL2 2 SDATA I C SCLK Logic Cypress Semiconductor Corporation Document #: 38-07638 Rev. *C Clock Generator for ATI 2 • support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 3.3V power supply • 56-pin SSOP and TSSOP packages ...

Page 2

Pin Description Pin No. Name 41,40,45,44 CPUT/C O, DIF Differential CPU clock outputs. AMD K8 buffer (200 Mhz). 50 PCI0 37 IREF 52, 53, 54 REF[2: 14.318-MHz REF clock output. Intel 7 SCLK 8 SDATA I/O,PU SMBus-compatible SDATA.This ...

Page 3

Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The ...

Page 4

Table 3. Byte Read and Byte Write Protocol (continued) Byte Write Protocol Bit Description 18:11 Command Code – 8 bits 19 Acknowledge from slave 27:20 Data byte – 8 bits 28 Acknowledge from slave 29 Stop Control Registers Byte 0:Control ...

Page 5

Byte 2: Control Register 2 Bit @Pup Name 7 1 CPUT/C SRCT USB_48 5 1 PCI 4 0 Reserved 3 1 Reserved 2 0 CPU SRC 1 1 Reserved 0 1 Reserved Byte 3: Control Register 3 Bit ...

Page 6

Byte 4: Control Register 4 (continued) Bit @Pup Name 0 1 Reserved Byte 5: Control Register 5 Bit @Pup Name 7 0 SRC[T/C SRC[T/C SRC[T/C SRC[T/C SRC[T/C SRC[T/C ...

Page 7

Table 4. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap 14.31818 MHz AT Parallel Crystal Recommendations The CY28RS480 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28RS480 to operate at the wrong frequency and violate ...

Page 8

CLK_REQ[0:1]# Description The CLKREQ#[1:0] signals are active low input used for clean stopping and starting selected SRC outputs. The outputs controlled by CLKREQ#[1:0] are determined by the settings in register bytes 4 and 5. The CLKREQ# signal is a debounced ...

Page 9

Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DDA V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J ESD ESD Protection (Human Body Model) HBM Ø ...

Page 10

AC Electrical Specifications (continued) Parameter Description XIN Rise and Fall Times XIN Cycle to Cycle Jitter CCJ L Long-term Accuracy ACC CPU Outputs T /T Output Slew Rate Differential Voltage DIFF ...

Page 11

AC Electrical Specifications (continued) Parameter Description PCI T PCI Duty Cycle DC T Spread Disabled PCI Period PERIOD T Spread Enabled PCI Period, SSC PERIODSS T Spread Disabled PCI Period PERIODAbs T Spread Enabled PCI Period, SSC PERIODSSAbs T PCI ...

Page 12

Test and Measurement Set-up For PCI Single-ended Signals and Reference The following diagram shows the test load configurations for the single-ended PCI, USB, and REF output signals. PCI/ USB REF For Differential CPU and SRC Output Signals The following diagram ...

Page 13

... Ordering Information Part Number Lead-free CY28RS480OXC 56-pin SSOP CY28RS480OXCT 56-pin SSOP – Tape and Reel CY28RS480ZXC 56-pin TSSOP CY28RS480ZXCT 56-pin TSSOP – Tape and Reel Package Drawing and Dimensions 56-Lead Shrunk Small Outline Package O56 28 29 0.720 0.730 0.088 0.092 ...

Page 14

... Document #: 38-07638 Rev. *C © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

Page 15

Document History Page Document Title: CY28RS480 Clock Generator for ATI Document Number: 38-07638 REV. ECN NO. Issue Date ** 204582 See ECN *A 215828 See ECN *B 267850 See ECN *C 325360 See ECN Document #: 38-07638 Rev. *C  ...

Related keywords