CY26114ZC Cypress Semiconductor Corp, CY26114ZC Datasheet

Page 1

... Cypress Semiconductor Corporation Document #: 38-07098 Rev. *B One-PLL Clock Generator Benefits ■ Internal PLL with up to 333 MHz internal operation. ■ Meets critical timing requirements in complex system designs. ■ Enables application compatibility. Output Frequency Range 2 copies of 100 MHz, 1 copy of 50 MHz, 1 copy 25, 33, 50, and 66 MHz (frequency selectable) Φ ...

Page 2

Pin Configurations Table 1. Pin Definitions Name Pin Number XIN FS0 SSL LCLK1 7 LCLK2 8 N/C 9 FS1 DDL N/C 12 VSS 13 ...

Page 3

Absolute Maximum Conditions Parameter V Supply Voltage Supply Voltage DDL T Junction Temperature J Digital Inputs Digital Outputs Referred to V Digital Outputs Referred to V Electro-Static Discharge Recommended Operating Conditions Parameter V Operating Voltage DD V ...

Page 4

... CLK CLK V DD 0.1 μ 0.1 μF Ordering Information Ordering Code Package Name CY26114ZC [3] Z16 CY26114KZC Z16 CY26114KZCT Z16 Note 3. Not recommended for new designs. Document #: 38-07098 Rev. *B Figure 2. Duty Cycle Definitions t2/ 50% 50% Figure 3. Rise Time and Fall Time Definitions t3 t4 ...

Page 5

... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...