DS1340C-18# Maxim Integrated Products, DS1340C-18# Datasheet - Page 11

• Manufacturer Part Number: DS1340C-18#
• Description: IC RTC I2C W/CHARGER 16-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/Trickle-Chargerr

Specifications of DS1340C-18#

• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.71 V ~ 1.89 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

have a one-second interval where the calibration is per-
formed. Negative calibration blanks 128 cycles of the
32,768Hz oscillator, slowing the clock down. Positive
calibration inserts 256 cycles of the 32,768Hz oscillator,
speeding the clock up. If a binary 1 is loaded into the
calibration bits, only the first two minutes in the 64-
minute cycle are modified. If a binary 6 is loaded, the
first 12 minutes are affected, and so on. Therefore,
each calibration step either adds 512 or subtracts 256
oscillator cycles for every 125,829,120 actual 32,678Hz
oscillator cycles (64 minutes). This equates to
+4.068ppm or -2.034ppm of adjustment per calibration
step. If the oscillator runs at exactly 32,768Hz, each of
the 31 increments of the calibration bits would repre-
sent +10.7 or -5.35 seconds per month, corresponding
to +5.5 or -2.75 minutes per month.
For example, if using the FT function, a reading of
512.01024Hz would indicate a +20ppm oscillator fre-
quency error, requiring a -10(00 1010) value to be
loaded in the S bit and the five calibration bits.
Note: Setting the calibration bits does not affect the fre-
quency test output frequency. Also note that writing to
the control register resets the divider chain.
The DS1340 supports a bidirectional I
transmission protocol. A device that sends data onto
the bus is defined as a transmitter and a device receiv-
ing data as a receiver. The device that controls the
message is called a master. The devices that are con-
trolled by the master are slaves. A master device that
generates the serial clock (SCL), controls the bus
access, and generates the START and STOP condi-
tions must control the bus. The DS1340 operates as a
Figure 7. I
SDA
SCL
IDLE
2
C Data Transfer Overview
CONDITION
START
I 2 C Serial Data Bus
ADDRESS
MSB FIRST
SLAVE
1–7
R/W
8
____________________________________________________________________
2
ACK
C bus and data
9
I
2
C RTC with Trickle Charger
MSB
1–7
REPEATED IF MORE BYTES
ARE TRANSFERRED
DATA
LSB
slave on the I
through the open-drain I/O lines SDA and SCL. Within
the bus specifications a standard mode (100kHz max
clock rate) and a fast mode (400kHz max clock rate)
are defined. The DS1340 works in both modes.
The following bus protocol has been defined (Figure 7):
Accordingly, the following bus conditions have been
defined:
8
• Data transfer can be initiated only when the bus is
• During data transfer, the data line must remain
not busy.
stable whenever the clock line is high. Changes in
the data line while the clock line is high are inter-
preted as control signals.
Bus not busy: Both data and clock lines remain
high.
START data transfer: A change in the data line’s
state from high to low, while the clock line is high,
defines a START condition.
STOP data transfer: A change in the data line’s
state from low to high, while the clock line is high,
defines a STOP condition.
Data valid: The data line’s state represents valid
data when, after a START condition, the data line is
stable for the duration of the high period of the
clock signal. The data on the line must be changed
during the low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a START condi-
tion and terminated with a STOP condition. The
number of data bytes transferred between the
START and STOP conditions is not limited, and is
ACK
9
2
C bus. Connections to the bus are made
MSB
1–7
DATA
LSB
8
NACK
ACK/
9
STOP CONDITION
REPEATED START
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