MAX5865ETM+ Maxim Integrated Products, MAX5865ETM+ Datasheet

MAX5865ETM+

Manufacturer Part Number

MAX5865ETM+

Description

IC ANLG FRONT END 40MSPS 48-TQFN

Manufacturer

Maxim Integrated Products

Datasheet

1.MAX5865ETM.pdf (26 pages)

Specifications of MAX5865ETM+

Number Of Bits

Number Of Channels

Power (watts)

2.10W

Voltage - Supply, Analog

2.7 V ~ 3.3 V

Voltage - Supply, Digital

1.8 V ~ 3.3 V

Package / Case

48-TQFN Exposed Pad

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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The MAX5865 ultra-low-power, highly integrated analog

front end is ideal for portable communication equipment

such as handsets, PDAs, WLAN, and 3G wireless termi-

nals. The MAX5865 integrates dual 8-bit receive ADCs

and dual 10-bit transmit DACs while providing the high-

est dynamic performance at ultra-low power. The ADCs’

analog I-Q input amplifiers are fully differential and

accept 1V

phase matching is ±0.2° and amplitude matching is

±0.05dB. The ADCs feature 48.4dB SINAD and 70dBc

spurious-free dynamic range (SFDR) at f

differential with ±400mV full-scale output, and 1.4V com-

mon-mode level. Typical I-Q channel phase matching is

±0.15° and gain matching is ±0.05dB. The DACs also

feature dual 10-bit resolution with 72dBc SFDR, and

57dB SNR at f

The ADCs and DACs operate simultaneously or indepen-

dently for frequency-division duplex (FDD) and time-divi-

sion duplex (TDD) modes. A 3-wire serial interface

controls power-down and transceiver modes of opera-

tion. The typical operating power is 75.6mW at f

40Msps with the ADCs and DACs operating simultane-

ously in transceiver mode. The MAX5865 features an

internal 1.024V voltage reference that is stable over the

entire operating power-supply range and temperature

range. The MAX5865 operates on a +2.7V to +3.3V ana-

log power supply and a +1.8V to +3.3V digital I/O power

supply for logic compatibility. The quiescent current is

8.5mA in idle mode and 1µA in shutdown mode. The

MAX5865 is specified for the extended (-40°C to +85°C)

temperature range and is available in a 48-pin thin QFN

package.

19-2916; Rev 1; 10/03

*EP = Exposed paddle.

**Contact factory for dice specifications.

Pin Configuration appears at end of data sheet.

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

CLK

MAX5865ETM

MAX5865E/D

PART

= 40MHz. The DACs’ analog I-Q outputs are fully

Narrowband/Wideband CDMA Handsets

and PDAs

Fixed/Mobile Broadband Wireless Modems

3G Wireless Terminals

P-P

OUT

full-scale signals. Typical I-Q channel

________________________________________________________________ Maxim Integrated Products

= 2.2MHz and f

-40°C to +85°C

Performance, 40Msps Analog Front End

TEMP RANGE

Ordering Information

General Description

CLK

Applications

= 40MHz.

Ultra-Low-Power, High-Dynamic-

PIN-PACKAGE

48 Thin QFN-EP*

(7mm x 7mm)

Dice**

= 5.5MHz and

CLK

o Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs

o Ultra-Low Power

o Excellent Dynamic Performance

o Excellent Gain/Phase Match

o Internal/External Reference Option

o +1.8V to +3.3V Digital Output Level (TTL/CMOS

o Multiplexed Parallel Digital Input/Output for

o Miniature 48-Pin Thin QFN Package (7mm

o Evaluation Kit Available (Order MAX5865EVKIT)

Compatible)

ADCs/DACs

75.6mW at f

64mW at f

Low-Current Idle and Shutdown Modes

48.4dB SINAD at f

70dB SFDR at f

±0.2° Phase, ±0.05dB Gain at f

REFIN

REFN

REFP

COM

QA+

QD+

QD-

QA-

IA+

ID+

ID-

IA-

CLK

REF AND

BIAS

= 22MHz (Transceiver Mode)

ADC

DAC

OUT

= 40MHz (Transceiver Mode)

MAX5865

Functional Diagram

= 2.2MHz (DAC)

= 5.5MHz (ADC)

AND SYSTEM

INTERFACE

CONTROL

SERIAL

OUTPUT

INPUT

MUX

ADC

MUX

DAC

= 5.5MHz (ADC)

Features

DA0–DA7

CLK

DD0–DD9

DIN

SCLK

7mm)

Related parts for MAX5865ETM+

MAX5865ETM+ Summary of contents

Page 1

... Exposed paddle. **Contact factory for dice specifications. Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Ultra-Low-Power, High-Dynamic- o Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs o Ultra-Low Power 75 ...

Page 2

Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End ABSOLUTE MAXIMUM RATINGS V to GND OGND................................-0.3V to +3. GND to OGND.......................................................-0.3V to +0.3V IA+, IA-, QA+, QA-, ID+, ID-, QD+, QD-, REFP, REFN, REFIN, COM to GND ..............................-0.3V ...

Page 3

Performance, 40Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C otherwise noted. Typical values are ...

Page 4

Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C otherwise noted. Typical values are at ...

Page 5

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Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End ( 3V 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output ...

Page 9

Performance, 40Msps Analog Front End ( 3V 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output 0.33µF, Xcvr ...

Page 10

Page 11

Performance, 40Msps Analog Front End ( 3V 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output 0.33µF, Xcvr ...

Page 12

Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End PIN NAME 1 REFP Upper Reference Voltage. Bypass with a 0.33µF capacitor to GND as close to REFP as possible. Analog Supply Voltage. Bypass 0.1µF capacitor. 3 ...

Page 13

Performance, 40Msps Analog Front End Detailed Description The MAX5865 integrates dual 8-bit receive ADCs and dual 10-bit transmit DACs while providing ultra-low power and highest dynamic performance at a conver- sion rate of 40Msps. The ADCs’ analog input amplifiers are ...

Page 14

Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End The ADC uses a seven-stage, fully differential, pipelined architecture that allows for high-speed con- version while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. ...

Page 15

Performance, 40Msps Analog Front End ADC System Timing Requirements Figure 3 shows the relationship between the clock, ana- log inputs, and the resulting output data. Channel IA (CHI) and channel QA (CHQ) are simultaneously sam- pled on the rising edge ...

Page 16

Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End Table 2. DAC Output Voltage vs. Input Codes (Internal Reference Mode V 1.024V, External Reference Mode V DIFFERENTIAL OUTPUT VOLTAGE V 1023 REFDAC × 2.56 1023 V 1021 REFDAC × 2.56 1023 V ...

Page 17

Performance, 40Msps Analog Front End Table 3. MAX5865 Operation Modes FUNCTION DESCRIPTION D evi ce shutd off off, and the ...

Page 18

Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End CSS CP SCLK t DS DIN MSB t DH Figure 5. 3-Wire Serial Interface Timing Diagram CS SCLK DIN 8-BIT DATA DAO–DA7 ID/QD Figure 6. MAX5865 Mode Recovery Timing Diagram ...

Page 19

Performance, 40Msps Analog Front End Clock jitter is especially critical for undersampling applications. Consider the clock input as an analog input and route away from any analog input or other digital signal lines. The MAX5865 clock input operates with an ...

Page 20

Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End ID+ MAX5865 ID- QD+ QD- Figure 8. Balun-Transformer Coupled Differential to Single- Ended Output Drive for DACs REFP 1kΩ ISO IN 0.1µF 50Ω 22pF 100Ω 1kΩ REFN 0.1µF R ...

Page 21

Performance, 40Msps Analog Front End R1 600Ω R2 600Ω R3 600Ω Figure 10. ADC DC-Coupled Differential Drive T/R Figure 11. Typical Application Circuit for TDD ______________________________________________________________________________________________________ Ultra-Low-Power, High-Dynamic 600Ω 600Ω R ISO 22Ω 600Ω 600Ω R8 ...

Page 22

Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End range, it can interface directly with RF transceivers while eliminating discrete components and amplifiers used for level-shifting circuits. Also, the DAC’s full dynamic range is preserved because the internally generated common- mode level ...

Page 23

Performance, 40Msps Analog Front End Offset error (Figure 12a) is the difference between the ideal and actual offset point. The offset point is the out- put value when the digital input is midscale. This error affects all codes by the ...

Page 24

Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End Power-Supply Rejection Power-supply rejection is defined as the shift in offset and gain error when the power supply is changed ±5%. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ...

Page 25

Performance, 40Msps Analog Front End (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) D D/2 ______________________________________________________________________________________ Ultra-Low-Power, High-Dynamic- k E/2 (NE- DETAIL ...

Page 26

... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Package Information (continued) ** NOTE: T4877 CUSTOM 48L PKG ...

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