MAX5863ETM+ Maxim Integrated Products, MAX5863ETM+ Datasheet
MAX5863ETM+
Specifications of MAX5863ETM+
Related parts for MAX5863ETM+
MAX5863ETM+ Summary of contents
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... Exposed paddle. **Contact factory for dice specifications. Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Ultra-Low-Power, High-Dynamic o Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs o Ultra-Low Power 22 ...
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Ultra-Low-Power, High-Dynamic Performance, 7.5Msps Analog Front End ABSOLUTE MAXIMUM RATINGS V to GND OGND................................-0.3V to +3. GND to OGND.......................................................-0.3V to +0.3V IA+, IA-, QA+, QA-, ID+, ID-, QD+, QD-, REFP, REFN, REFIN, COM to GND ..............................-0.3V ...
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Performance, 7.5Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C otherwise noted. Typical values are ...
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Ultra-Low-Power, High-Dynamic Performance, 7.5Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C otherwise noted. Typical values are at ...
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Performance, 7.5Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C otherwise noted. Typical values are ...
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Ultra-Low-Power, High-Dynamic Performance, 7.5Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C otherwise noted. Typical values are at ...
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Performance, 7.5Msps Analog Front End ELECTRICAL CHARACTERISTICS (continued 3V 1.8V, internal reference (1.024V DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C otherwise noted. Typical values are ...
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Ultra-Low-Power, High-Dynamic Performance, 7.5Msps Analog Front End ( 3V 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output ...
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Performance, 7.5Msps Analog Front End ( 3V 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output 0.33µF, Xcvr ...
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Ultra-Low-Power, High-Dynamic Performance, 7.5Msps Analog Front End ( 3V 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output ...
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Performance, 7.5Msps Analog Front End ( 3V 1.8V, internal reference (1.024V input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output 0.33µF, Xcvr ...
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Ultra-Low-Power, High-Dynamic Performance, 7.5Msps Analog Front End PIN NAME 1 REFP Upper Reference Voltage. Bypass with a 0.33µF capacitor to GND as close to REFP as possible. Analog Supply Voltage. Bypass 0.1µF capacitor. 3 ...
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Performance, 7.5Msps Analog Front End Detailed Description The MAX5863 integrates dual 8-bit receive ADCs and dual 10-bit transmit DACs while providing ultra-low power and highest dynamic performance at a conver- sion rate of 7.5Msps. The ADCs’ analog input amplifiers are ...
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Ultra-Low-Power, High-Dynamic Performance, 7.5Msps Analog Front End The ADC uses a seven-stage, fully differential, pipelined architecture that allows for high-speed con- version while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. ...
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Performance, 7.5Msps Analog Front End ADC System Timing Requirements Figure 3 shows the relationship between the clock, ana- log inputs, and the resulting output data. Channel IA (CHI) and channel QA (CHQ) are simultaneously sam- pled on the rising edge ...
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Ultra-Low-Power, High-Dynamic Performance, 7.5Msps Analog Front End Table 2. DAC Output Voltage vs. Input Codes (Internal Reference Mode V 1.024V, External Reference Mode V DIFFERENTIAL OUTPUT VOLTAGE V 1023 REFDAC × 2.56 1023 V 1021 REFDAC × 2.56 1023 V ...
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Performance, 7.5Msps Analog Front End Table 3. MAX5863 Operation Modes FUNCTION DESCRIPTION D evi ce shutd off off, and the ...
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Ultra-Low-Power, High-Dynamic Performance, 7.5Msps Analog Front End CSS CP SCLK t DS DIN MSB t DH Figure 5. 3-Wire Serial Interface Timing Diagram CS SCLK DIN 8-BIT DATA DAO–DA7 ID/QD Figure 6. MAX5863 Mode Recovery Timing Diagram ...
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Performance, 7.5Msps Analog Front End where f represents the analog input frequency and the time of the clock jitter. AJ Clock jitter is especially critical for undersampling applications. Consider the clock input as an analog input and ...
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Ultra-Low-Power, High-Dynamic Performance, 7.5Msps Analog Front End ID+ MAX5863 ID- QD+ QD- Figure 8. Balun-Transformer Coupled Differential to Single- Ended Output Drive for DACs REFP 1kΩ ISO IN 0.1µF 50Ω 22pF 100Ω 1kΩ REFN 0.1µF R ...
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Performance, 7.5Msps Analog Front End Figure 10. ADC DC-Coupled Differential Drive T/R Figure 11. Typical Application Circuit for TDD mode ______________________________________________________________________________________________________ Ultra-Low-Power, High-Dynamic R4 R5 600Ω 600Ω R1 600Ω R2 600Ω 600Ω 600Ω R3 600Ω 600Ω ...
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Ultra-Low-Power, High-Dynamic Performance, 7.5Msps Analog Front End with RF quadrature modulators while eliminating dis- crete components and amplifiers used for level-shifting circuits. Also, the DAC’s full dynamic range is pre- served because the internally generated common- mode level eliminates code-generated ...
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Performance, 7.5Msps Analog Front End Ideally, the midscale transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured transition point and the ideal transition point. Offset error is the difference between the ...
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Ultra-Low-Power, High-Dynamic Performance, 7.5Msps Analog Front End Power-Supply Rejection Power-supply rejection is defined as the shift in offset and gain error when the power supply is changed ±5%. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ...
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Performance, 7.5Msps Analog Front End (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) D D/2 ______________________________________________________________________________________ Ultra-Low-Power, High-Dynamic k E/2 (NE- DETAIL ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Package Information (continued) ** NOTE: T4877 CUSTOM 48L PKG ...