AD9879BS Analog Devices Inc, AD9879BS Datasheet - Page 24

• Manufacturer Part Number: AD9879BS
• Description: IC FRONT-END MIXED-SGNL 100-MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9879BS

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Number Of Channels: 5
• Power (watts): 587mW
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 100-MQFP, 100-PQFP

AD9879
Tx SIGNAL LEVEL CONSIDERATIONS
The quadrature modulator introduces a maximum gain of 3 dB
in signal level. To visualize this, assume that both the I data and
Q data are fixed at the maximum possible digital value, x. The
output of the modulator, z is then:
It can be shown that |z| assumes a maximum value of
However, if the same number of bits are used to represent the |z|
values, as is used to represent the x values, an overflow occurs.
To prevent this possibility, an effective −3 dB attenuation is
internally implemented on the I and Q data path.
Table 11. I–Q Input Test Signals
Analog Output
Single Tone (f
Single Tone (f
Dual Tone (f
z = [x cos(ωt) – x sin(ωt)]
(
z
z
=
=
AD9879
DAC
(
x
C
(
1
± f)
2
C
C
2 /
– f)
+ f)
+
Figure 17. 16-Quadrature Modulation
Figure 18. 16-Quadrature Modulation
x
+
2
1
)
2 /
TX
=
CA
)
x
=
CA_EN
CA_DATA
CA_CLK
LOW-PASS
2
x
FILTER
)
(
3
a
X
Digital Input
I = cos(f)
Q = cos(f + 90°) = −sin(f)
I = cos(f)
Q = cos(f + 270°) = +sin(f)
I = cos(f)
Q = cos(f + 180°) = −cos(f) or Q = +cos(f)
O
gain
X
Z
of
+
I
VARIABLE GAIN
CABLE DRIVER
3
AMPLIFIER
dB
AD832x
)
75Ω
(17)
(18)
(19)
Rev. A | Page 24 of 32
The following example assumes a PK/rms level of 10 dB:
The maximum complex input rms value calculation uses both
I and Q symbol components that add a factor of 2 (6 dB) to the
formula.
Table 11 shows typical I-Q input test signals with amplitude
levels related to 12-bit full scale (FS).
Tx THROUGHPUT AND LATENCY
Data inputs impact the output fairly quickly but remain
effective due to the filter characteristics of the AD9879. Data
transmit latency through the AD9879 is easiest to describe in
terms of f
when an effect is first seen after an input value changes.
Latency of I/Q data entering the data assembler (AD9879 input)
to the DAC output is 119 f
DC values applied to the data assembler input takes up to 176
f
DAC output.
Frequency hopping is accomplished via changing the PROFILE
input pin. The time required to switch from one frequency to
another is less than 232 f
SYSCLK
Maximum Symbol Component Input Value =
±(2,047 LSBs − 0.2 dB) = ±2,000 LSBs
Maximum Complex Input RMS Value =
2,000 LSBs + 6 dB − Pk/rms (dB) = 1,265 LSBs rms
clock cycles (44 f
SYSCLK
Input Level
FS – 0.2 dB
FS – 0.2 dB
FS – 0.2 dB
FS – 0.2 dB
FS – 0.2 dB
FS – 0.2 dB
clock cycles (4 f
MCLK
SYSCLK
SYSCLK
cycles) to propagate and settle at the
cycles (58.5 f
MCLK
Modulator Output Level
FS – 3.0 dB
FS – 3.0 dB
FS
clock cycles (29.75 f
). The numbers quoted are
MCLK
cycles).
MCLK
cycles).
(20)
(21)