LTC1603CG#PBF Linear Technology, LTC1603CG#PBF Datasheet
LTC1603CG#PBF
Specifications of LTC1603CG#PBF
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LTC1603CG#PBF Summary of contents
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... The ADC has P compatible,16-bit parallel output port. There is no pipeline delay in conversion results. A separate convert start input and a data ready signal (BUSY) ease connections to FlFOs, DSPs and microprocessors. , LTC and LT are registered trademarks of Linear Technology Corporation 2 ...
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LTC1603 ABSOLUTE MAXIMUM (Notes Supply Voltage (V ) ................................................ 6V DD Negative Supply Voltage (V ) ............................... – Total Supply Voltage (V ...
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ACCURACY otherwise specifications are (Note 5) A SYMBOL PARAMETER S/N Signal-to-Noise Ratio S/( Signal-to-(Noise + Distortion) Ratio THD Total Harmonic Distortion Up to 5th Harmonic SFDR Spurious Free ...
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LTC1603 W U POWER REQUIRE E TS range, otherwise specifications are at T SYMBOL PARAMETER V Positive Supply Voltage DD V Negative Supply Voltage SS I Positive Supply Current DD Nap Mode Sleep Mode I Negative Supply Current SS Nap ...
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CHARACTERISTICS Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND, OGND and AGND wired ...
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LTC1603 PIN FUNCTIONS + A (Pin 1): Positive Analog Input. The ADC converts the IN + difference voltage between A and tial range of 2.5V. A has a 2.5V input range when IN – ...
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CTIO AL BLOCK DIAGRA 3 V REFCOMP DIFFERENTIAL ANALOG INPUT – 2.5V IN TEST CIRCUITS Load Circuits for Access Timing (A) Hi-Z TO ...
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LTC1603 U U APPLICATIONS INFORMATION CONVERSION DETAILS The LTC1603 uses a successive approximation algorithm and internal sample-and-hold circuit to convert an analog signal to a 16-bit parallel output. The ADC is complete with a sample-and-hold, a precision reference and an ...
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U U APPLICATIONS INFORMATION SHDN Figure 2a. Nap Mode to Sleep Mode Timing SHDN t 4 CONVST Figure 2b. SHDN to CONVST Wake-Up Timing CONVST Figure CONVST Setup ...
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LTC1603 U U APPLICATIONS INFORMATION CONVST t 6 BUSY DATA (N – 1) DATA D15 TO D0 Figure 5. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled (CONVST = CS = ...
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U U APPLICATIONS INFORMATION CONVST t 6 BUSY t 10 DATA CONVST t 6 BUSY DATA three-state until read by the MPU with the RD signal. Mode 2 can be ...
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... DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC1603. More detailed informa- tion is available in the Linear Technology databooks, the TM LinearView CD-ROM and on our web site at: www ...
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U U APPLICATIONS INFORMATION 100 1 ANALOG INPUT A 3000pF REFCOMP AGND Figure 11. RC Input Filter Input Range The 2.5V input range of the LTC1603 is optimized for low noise and ...
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LTC1603 U U APPLICATIONS INFORMATION ANALOG INPUT 2V TO 2.7V DIFFERENTIAL 2V TO 2.7V LTC1450 47 F Figure 13. Driving V with a DAC REF 10k 100k INPUT FREQUENCY (Hz) ...
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U U APPLICATIONS INFORMATION –5V ANALOG INPUT R3 24k R8 50k R4 100 R5 R7 47k 50k R6 24k + 0 Figure 15b. Offset and Full-Scale Adjust Circuit + – (i.e., – 0.5LSB ...
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LTC1603 U U APPLICATIONS INFORMATION – REF 2 ANALOG + INPUT – CIRCUITRY 2 PERFORMANCE The noise of an ADC can be evaluated in two ways: signal- to-noise raio (SNR) in ...
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U U APPLICATIONS INFORMATION Signal-to-Noise Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The ...
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LTC1603 U U APPLICATIONS INFORMATION Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal ...
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... FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. ...
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... Low Power, Low Gritch, 4-Quadrant Multiplication www.linear.com DGND DD DD SHDN CONTROL LOGIC CONVST 31 CONTROL AND 2. LINES TIMING REF BUSY OGND 28 OUTPUT B15 TO B0 16-BIT BUFFERS D15 TO D0 PARALLEL BUS LTC1603 AGND 1603 TA03 –5V LT/TP 0503 1K • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2003 1603f ...