CS5343-CZZ Cirrus Logic Inc, CS5343-CZZ Datasheet - Page 14

• Manufacturer Part Number: CS5343-CZZ
• Description: IC ADC AUD 98DB 108KHZ 10-TSSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5343-CZZ

• Package / Case: 10-TSSOP
• Number Of Converters: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 108k
• Data Interface: Serial
• Power Dissipation (max): 85mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Conversion Rate: 96 KSPS
• Resolution: 24 bit
• Number Of Adc Inputs: 2
• Operating Supply Voltage: 3.3 V or 5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Power Consumption: 40 mW
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 3.1 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1156 - BOARD EVAL FOR CS5343 STEREO ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1189

14
4.1.2
4.1.3
4.1.2.1
Master Mode Operation
As clock Master, the CS5343/4 generates LRCK and SCLK synchronously on-chip.
available sample rates and associated clock ratios in Master Mode.
During power-up in Master Mode, the LRCK and SCLK pins are inputs to configure speed mode and the
output clock ratio. The LRCK pin is pulled low internally to select Single-Speed Mode by default, but Dou-
ble-Speed Mode is accessed with a 10 kΩ pull-up resistor from LRCK to VA as shown in
larly, the SCLK pin is internally pulled-low by default to select a 256x/512x MCLK/LRCK ratio, but a
MCLK/LRCK ratio of 348x/768x is accessed with a 10 kΩ pull-up resistor from SCLK to VA as shown in
Table
Master Clock
The CS5343/4 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters.
There is an internal automatic MCLK divider which is activated based on the input frequency of MCLK.
This divider selection allows the high and low MCLK speeds in a given speed mode (i.e. 256x and 512x
in SSM).
LRCK
SCLK
32 (*Slave Mode Only)
Double-Speed Mode
Pin
Sample Rate (kHz)
Sample Rate (kHz)
Single-Speed Mode
4. Following the power-up routine, the LRCK and SCLK pins become clock outputs.
Speed Mode
Table 4
Master Mode Speed Selection
44.1
88.2
48
96
Table 3. Speed Modes and the Associated Sample Rates (Fs) in Master Mode
lists some common audio output sample rates and the required MCLK frequency.
Internal Pull-Down to GND (100 kΩ)
Internal Pull-Down to GND (100 kΩ)
Table 5. Common MCLK Frequencies in Master and Slave Modes
External Pull-Up to VA (10 kΩ)
External Pull-Up to VA (10 kΩ)
Resistor Option
Table 4. Speed Mode Selection in Master Mode
MCLK/LRCK
Speed Mode
Speed Mode
Ratio
256x
512x
384x
768x
128x
256x
192x
384x
SSM
SSM
SSM
DSM
DSM
Master and Slave Mode
4/2/08
Draft
SCLK/LRCK
11.289
12.288
11.289
12.288
*8.912
Ratio
256x
128x
64
64
64
64
64
64
64
64
MCLK(MHz)
MCLK(MHz)
128x/256x/512x MCLK/LRCK (default)
*16.384
22.579
24.576
22.579
24.576
512x
256x
Input Sample Rate Range (kHz)
192x/384x/768x MCLK/LRCK
Single-Speed Mode (default)
Clock Configuration
Double-Speed Mode
*12.288
16.934
18.432
16.934
18.432
86 - 108
86 - 108
86 - 108
86 - 108
43 - 54
43 - 54
43 - 54
43 - 54
384x
192x
MCLK (MHz)
MCLK (MHz)
Table 3
CS5343/4
Table
shows the
*24.576
33.868
36.864
33.868
36.864
DS687F3
768x
384x
4. Simi-