CS5528-ASZ Cirrus Logic Inc, CS5528-ASZ Datasheet
CS5528-ASZ
Specifications of CS5528-ASZ
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CS5528-ASZ Summary of contents
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... The ADCs come as either (CS5523/24), or eight-channel (CS5528) devices and include a low-input-current, chopper-stabilized instru- mentation amplifier. To permit selectable input spans of 25 mV, 55 mV, 100 mV 2.5 V, and 5 V, the ADCs include a PGA (programmable gain amplifier) ...
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TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5 ANALOG CHARACTERISTICS ................................................................................................ 5 TYPICAL RMS NOISE, CS5521/23.......................................................................................... 7 TYPICAL NOISE FREE RESOLUTION (BITS), CS5521/23 .................................................... 7 TYPICAL RMS NOISE, CS5522/24/28..................................................................................... 8 TYPICAL NOISE FREE RESOLUTION (BITS), CS5522/24/28 ............................................... 8 5 ...
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Unipolar/Bipolar Bit ............................................................................. 28 2.2.8 Configuration Register ........................................................................................ 28 2.2.8.1 Chop Frequency Select ...................................................................... 28 2.2.8.2 Conversion/Calibration Control Bits .................................................... 28 2.2.8.3 Power Consumption Control Bits ........................................................ 28 2.2.8.4 Charge Pump Disable ......................................................................... 29 2.2.8.5 Reset System Control Bits ...
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LIST OF FIGURES Figure 1. Continuous Running SCLK Timing (Not to Scale) ......................................................... 12 Figure 2. SDI Write Timing (Not to Scale) ..................................................................................... 12 Figure 3. SDO Read Timing (Not to Scale) ................................................................................... 12 Figure 4. Multiplexer Configurations.............................................................................................. 13 Figure ...
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CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS NBV = -2.1 V, XIN = 32.768 kHz, CFS1-CFS0 = ‘00’, OWR (Output Word Rate Sps, Bipolar Mode, Input Range = ±100 mV; See Notes 1 and 2.) Parameter Accuracy Resolution Linearity ...
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... V 2 Notes: 7. For the CS5528, the 25 mV and 100 mV ranges cannot be used unless NBV is powered at -1 See the section of the data sheet which discusses input models. Chop clock is 256 Hz (XIN/128) for PGIA (programmable gain instrumentation amplifier). XIN = 32.768 kHz. 9. The maximum full scale signal can be limited by saturation of circuitry within the internal signal path. ...
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TYPICAL RMS NOISE, CS5521/23 Output Rate -3 dB Filter (Sps) Frequency 1.88 1.64 3.76 3.27 7.51 6.55 15.0 12.7 30.0 25.4 61.6 (Note 12) 50.4 84.5 (Note 12) 70.7 101.1 (Note 12) 84.6 Notes: 10. Wideband noise aliased into the ...
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TYPICAL RMS NOISE, CS5522/24/28 Output Rate -3 dB Filter (Sps) Frequency 1.88 1.64 3.76 3.27 7.51 6.55 15.0 12.7 30.0 25.4 61.6 (Note 16) 50.4 84.5 (Note 16) 70.7 101.1 (Note 16) 84.6 Notes: 14. Wideband noise aliased into the ...
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V DIGITAL CHARACTERISTICS See Notes 2 and 18.)) Parameter High-level Input Voltage All Pins Except XIN and SCLK Low-level Input Voltage All Pins Except XIN and SCLK High-level Output Voltage All Pins Except CPD and SDO (Note 19) Low-level ...
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DYNAMIC CHARACTERISTICS Parameter Modulator Sampling Frequency Filter Settling Time to 1/2 LSB (Full-scale Step) RECOMMENDED OPERATING CONDITIONS Parameter DC Power Supplies Analog Reference Voltage Negative Bias Voltage Notes: 20. All voltages with respect to ground. ABSOLUTE MAXIMUM RATINGS Parameter DC ...
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SWITCHING CHARACTERISTICS Levels: Logic Logic 1 = VD+; C Parameter Master Clock Frequency External Clock or Internal Oscillator (CS5522/24/28) Master Clock Duty Cycle Rise Times Any Digital Input Except SCLK Fall Times Any Digital Input Except ...
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Figure 1. Continuous Running SCLK Timing (Not to Scale ...
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... The ADCs come as either two-channel (CS5521/22), four-channel (CS5523/24), or eight- channel (CS5528) devices, and include a low input current, chopper-stabilized instrumentation ampli- fier. To permit selectable input spans of 25 mV, 55 mV, 100 mV 2.5 V, and 5 V, the ADCs in- clude a PGA (programmable gain amplifier) ...
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... CS5521/22/23/24/ operated in either of two analog input configurations. The NBV pin can be bi- ased to a negative voltage between -1.8 V and -2 tied to AGND (for the CS5528, NBV has to be between -1.8 V and -2.5 V for the ranges below 100 mV when the amplifier is engaged). The com- mon-mode-plus-signal range of the instrumentation amplifier is 1 ...
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Analog Input Span Considerations The CS5521/22/23/24/28 is designed to measure full-scale ranges of 25 mV, 55 mV, 100 mV 2.5 V, and 5 V. Other full scale values can be ac- commodated by performing a system calibration ...
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Figure 7 illustrates an example circuit. Re- fer to Application Note 158 for more details on high-voltage ...
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A group of registers, called Channel Set-up Regis- ters, are also included in the converters. These reg- isters are used to hold pre-loaded conversion instructions. Each channel set-up ...
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System Initialization When power to the CS5521/22/23/24/28 is applied, the chips are held in a reset condition until the 32.768 kHz oscillator has started and a counter- timer elapses. Due to the high Q of the 32.768 kHz crystal, ...
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... Read from selected register. 000 Reserved 001 Offset Register 010 Gain Register 011 Configuration Register 101 Channel Set-up Registers - register is 48-bits long for CS5521/22 - register is 96-bits long for CS5523/24 - register is 192-bits long for CS5528 110 Reserved 111 Reserved CSRP0 CC2 CC1 VALUE 0 See table above ...
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... Gain Register 1(All devices) 001 Gain Register 2 (All devices) 010 Gain Register 3 (CS5523/24/28 only) 011 Gain Register 4 (CS5523/24/28 only) 100 Gain Register 5 (CS5528 only) 101 Gain Register 6 (CS5528 only) 110 Gain Register 7 (CS5528 only) 111 Gain Register 8 (CS5528 only CS1 CS0 ...
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... CSRs accessed is determined by the device being used and the number of CSRs that are being accessed (i.e. the depth bits in the configuration register determine the number of levels ac- cessed). This register is 48-bits long (4 Setups) for the CS5521/22, 96-bits long (8 Setups) for the CS5523/24, and 192-bits (16 Setups) long for the CS5528. R/W (Read/Write) 0 Write to selected register ...
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... Setup 7 (CS5523/24/28) 0111 Setup 8 (CS5523/24/28) 1000 Setup 9 (CS5528 only) 1001 Setup 10 (CS5528 only) 1010 Setup 11 (CS5528 only) 1011 Setup 12 (CS5528 only) 1100 Setup 13 (CS5528 only) 1101 Setup 14 (CS5528 only) 1110 Setup 15 (CS5528 only) 1111 Setup 16 (CS5528 only CSRP1 CSRP0 CS5521/22/23/24/ ...
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... Setup 9 (CS5528 only) 1001 Setup 10 (CS5528 only) 1010 Setup 11 (CS5528 only) 1011 Setup 12 (CS5528 only) 1100 Setup 13 (CS5528 only) 1101 Setup 14 (CS5528 only) 1110 Setup 15 (CS5528 only) 1111 Setup 16 (CS5528 only) CC [2:0] (Calibration Control Bits) 000 Reserved 001 Self-Offset Calibration 010 ...
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SYNC1 D7(MSB Function: Part of the serial port re-initialization sequence. SYNC0 D7(MSB Function: End of the serial port re-initialization sequence. NULL D7(MSB Function: This command is used to clear a port ...
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Serial Port Interface The CS5521/22/23/24/28’s serial interface consists of four control lines: CS, SCLK, SDI, SDO. Figure 10 illustrates the serial sequence necessary to write to, or read from the serial port’s registers. CS (Chip Select) is the control ...
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... The CS5521/22 have two 24-bit channel-setup reg- isters (CSRs). The CS5523/24 have four CSRs, and the CS5528 has eight CSRs (refer to Table 3 for more detail on the CSRs). These registers are ac- cessed in conjunction with the depth pointer bits in the configuration register. Each CSR contains two ...
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... Select physical channel 5 (CS5528 only) 101 Select physical channel 6 (CS5528 only) 110 Select physical channel 7 (CS5528 only) 111 Select physical channel 8 (CS5528 only) 000 R 15.0 Sps (2180 XIN cycles). 001 30.0 Sps (1092 XIN cycles). 010 61.6 Sps (532 XIN cycles). ...
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Latch Outputs The A1-A0 pins mimic the latch output, D23/D11- D22/D10, bits of the channel-setup registers. A1-A0 can be used to control external multiplexers and oth- er logic functions outside the converter. The outputs can sink or source at ...
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CS5522/24/28 typically consume 9.0 mW. The CS5521/23 typically consume 6.0 mW. The low- power mode is an alternate mode in the CS5522/24/28 that reduces the consumed power to 5.5 mW entered by setting bit D8 (the low- power ...
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... Setups are converted when MC=1 and a command byte 1111 with its MSB = 1 is issued. Note that the CS5522 has two CSRS, the CS5524 has four CSRs, and the CS5528 has 8 CSRs Standby Mode (Oscillator active, allows quick power-up). ...
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... For self calibration of offset in the 25 mV, 55 mV, and 100 mv ranges, the con- verters internally tie the inputs of the instrumenta- tion amplifier together and route them to the AIN- pin as shown in Figure 11 (in the CS5528 they are routed to AGND). For proper self-calibration ...
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AIN- pin must be at the proper com- mon-mode voltage as specified in ‘Common Mode +Signal AIN+/-’ specification in the Analog Input section (if AIN- = ...
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In either case, the calibration signals must be within the specified calibration limits for each specific calibration step (refer to the ‘System Calibration Specifications’ in ANALOG CHARACTERISTICS system gain calibration is performed the ...
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... While reading, note that the CS5521/22 have a FIFO which is four words deep. The CS5523/24 have a FIFO which is eight words deep and the CS5528 has a FIFO which is sixteen -22 decimal) DS317F4 ...
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Further note that the type of conversion(s) performed and the way to access the resulting data from the FIFO is determined by the MC (multiple conversion), the LP (loop), the RC (read convert), and the DP (depth ...
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SDO line. If, during the first 8 SCLKs, "00000000" is provided on SDI, the converter will remain in this conversion mode, and continue to perform conversions on the selected Setup. To exit this conversion mode, "11111111" must be provid- ed ...
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Repeated Multiple-Setup Conversions without Wait ( this conversion mode, the ADC will repeatedly perform conversions, referencing multiple Setups. The CSRP bits in the command word are ignored in this mode. ...
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... Setups in the chan- nel-setup registers (CSRs). Five example situations that a user might encounter when acquiring a con- version or calibrating the converter follow. These examples assume that the user is using a CS5528 (16 Setups) and that its CSRs are programmed with the following physical channel order ...
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SD0. After ‘1111 1111’ is provided, 24 additional SCLKs are required to transfer the last 3 bytes of conversion data before the serial port will return to the command mode. Example 3: The configuration register has the following bits as ...
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Once the CSRs are programmed, repeated conver- sions Setups can be performed by is- suing only one command byte. 5) The single conversion mode also requires only one command, but whenever ...
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Conversion Data FIFO Descriptions CS5521/23 (EACH 16-BIT CONVERSIONS) D23 D22 D21 D20 D19 MSB D11 D10 LSB CS5522/24/28 (EACH 24-BIT CONVERSION LEVELS) D23 D22 D21 D20 D19 MSB 22 ...
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Digital Filter The CS5521/22/23/24/28 have eight different lin- ear phase digital filters which set the output word rates (OWRs) shown in Table 3. These rates as- sume that XIN is 32.768 kHz. Each of the filters has a magnitude ...
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Power Supply Arrangements The CS5521/22/23/24/28 A/D converters are de- signed to operate from a single +5 V analog supply and a single + digital supply. A -2.1 V supply is usually generated from the charge ...
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Figure 22. CS5522 Configured for ground-referenced Unipolar Signals + alo ...
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... CS5525/26 Charge Pump Drive for External Loads” for more details on using the charge pump with exter- nal loads. 2.9 Digital Gain Scaling The CS5521/22/23/24 and CS5528 all feature a gain register capable of being scaled from 0 - decimal. The specified ranges of the con- verter are defined with a voltage reference of 2 ...
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The converter input ranges are specified with a voltage reference of 2.5 V. The device can be op- erated ...
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Note that while the RS bit is set to ‘1’ all other register bits in the ADC will be reset to their default state, and the RS bit must be set to ‘0’ for normal operation of the ...
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... SERIAL DATA OUT 11 14 XIN XOUT CRYSTAL OUT 12 13 VOLTAGE REFERENCE INPUT AGND VREF VA+ VREF- VOLTAGE REFERENCE INPUT 2 23 CS5528 AIN1+ AIN3+ SINGLE-ENDED ANALOG INPUT 3 22 SINGLE-ENDED ANALOG INPUT AIN2+ AIN4 AIN5+ AIN7+ SINGLE-ENDED ANALOG INPUT 5 20 AIN6+ AIN8+ SINGLE-ENDED ANALOG INPUT ...
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... Differential input pins into the CS5522 and CS5524 devices. AIN1+, AIN2+, AIN3+, AIN4+, AIN5+, AIN6+, AIN7+, AIN8+ - Single-Ended Analog Input. Single-ended input pins into the CS5528. VREF+, VREF- - Voltage Reference Input. Fully differential inputs which establish the voltage reference for the on-chip modulator. ...
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... May be tied to AGND if AIN+ and AIN- inputs are centered around +2 may be tied to a negative supply voltage (-2.1 V typical) to allow the amplifier to handle low level signals more negative than ground. When using the CS5528 in either the 25 mV 100 mV range, the analog inputs are expected to be ground referenced; ...
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SPECIFICATION DEFINITIONS Linearity Error The deviation of a code from a straight line which connects the two endpoints of the A/D Converter transfer function. One endpoint is located 1/2 LSB below the first code transition and the other endpoint ...
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... Plastic DIP CS5524-AS 24-pin 0.2" Plastic SSOP CS5524-ASZ 24-pin 0.2" Plastic SSOP (Lead Free) CS5528-AS 24-pin 0.2" Plastic SSOP CS5528-ASZ 24-pin 0.2" Plastic SSOP (Lead Free) * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 52 CS5521/22/23/24/28 Bits Channels Linearity Error (Max) Temperature Range ± ...
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PACKAGE DIMENSION DRAWINGS 20 PIN PLASTIC (PDIP) (300 MIL) PACKAGE DRAWING E1 1 TOP VIEW DIM MIN A 0.000 A1 0.015 A2 0.115 b 0.014 b1 0.045 c 0.008 D 0.980 E 0.300 E1 0.240 e 0.090 eA 0.280 ...
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PIN SKINNY PLASTIC (PDIP) (300 MIL) PACKAGE DRAWING E1 1 TOP VIEW DIM MIN A 0.000 A1 0.015 A2 0.115 b 0.014 b1 0.045 c 0.008 D 1.230 E 0.300 E1 0.240 e 0.090 eA 0.280 eB 0.300 eC ...
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SSOP PACKAGE DRAWING TOP VIEW INCHES DIM MIN 0.002 A2 0.064 b 0.009 D 0.272 E 0.291 E1 0.197 e 0.022 L 0.025 ∝ 0° Notes: 1. “D” and “E1” are ...
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SSOP PACKAGE DRAWING TOP VIEW INCHES DIM MIN 0.002 A2 0.064 b 0.009 D 0.311 E 0.291 E1 0.197 e 0.022 L 0.025 ∝ 0° Notes: 1. “D” and “E1” are ...