AD7357BRUZ Analog Devices Inc, AD7357BRUZ Datasheet - Page 18

• Manufacturer Part Number: AD7357BRUZ
• Description: IC ADC DUAL14BIT 4.2MSPS 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7357BRUZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Design Resources: DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7357 (CN0061)
• Number Of Bits: 14
• Sampling Rate (per Second): 4.2M
• Number Of Converters: 2
• Power Dissipation (max): 59mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 14bit
• Input Channel Type: Differential
• Supply Voltage Range - Analogue: 2.25V To 2.75V
• Supply Voltage Range - Digital: 2.25V To 3.6V
• Supply: RoHS Compliant
• Sampling Rate: 4.2MSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7357
SERIAL INTERFACE
Figure 30 shows the detailed timing diagram for serial inter-
facing to the AD7357. The serial clock provides the conversion
clock and controls the transfer of information from the AD7357
during conversion. There is a single sample delay in the result
that is clocked out from the AD7357.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode
at which point the analog input is sampled and the bus is taken
out of three-state. The conversion is also initiated at this point
and requires a minimum of 16 SCLKs to complete. When 16
SCLK falling edges have elapsed, the track-and-hold goes back
into track on the next SCLK rising edge, as shown in
at Point B. On the rising edge of
and SDATA
brought high but is, instead, held low for an additional 16 SCLK
cycles on SDATA , the data from the conversion on ADC B
is output on SDATA
SDATA
SCLK
SDATA
SDATA
A
CS
A
and SDATA
SCLK
THREE-
STATE
CS
A
B
A
THREE-
STATE
A
.
t
2
2 LEADING
0
ZEROS
1
2 LEADING ZEROS
B
t
t
3
go back into three-state. If CS is not
2
0
0
1
CS , the conversion is terminated
t
2
3
DB13
0
A
2
Figure 31. Reading Data from Both ADCs on One SDATA Line with 32 SCLKs
3
DB13
DB12
A
4
3
DB11
DB12
t
t
6
4
A
Figure 30. Serial Interface Timing Diagram
t
5
5
4
Figure 30
DB11
t
t
6
4
15
t
CONVERT
Rev. A | Page 18 of 20
t
5
DB0
7
DB10
t
7
A
16
0
2 ZEROS
17
Likewise, if CS is held low for an additional 16 SCLK cycles on
SDATA
on SDATA
goes back into three-state on the 32
rising edge of
A minimum of 16 serial clock cycles are required to perform
the conversion process and to access data from one conversion
on either data line of the AD7357. Note that the data that is
accessed on SDATA
conversion. CS going low provides the leading zero to be read
in by the microcontroller or DSP. The remaining data is then
clocked out by subsequent SCLK falling edges, beginning with
a second leading zero. Thus, the first falling clock edge on the
serial clock has the leading zero provided and also clocks out
the second leading zero. The 14-bit result then follows with the
final bit in the data transfer valid on the 16
been clocked out on the previous (15
tions with a slower SCLK, it may be possible to read in data on
each SCLK rising edge depending on the SCLK frequency. The
first rising edge of SCLK after the CS falling edge has the second
leading zero provided, and the 15
provided.
0
DB2
18
DB13
A
, the data from the conversion on ADC A is output
t
B
5
B
(see
DB1
CS , whichever occurs first.
DB12
Figure 31
B
15
A
and SDATA
DB0
). In this case, the SDATA line in use
16
B
DB1
0
B
t
8
B
th
t
ACQUISITION
31
is the result of the previous
rising SCLK edge has DB0
nd
DB0
THREE-STATE
th
SCLK falling edge or the
) falling edge. In applica-
t
B
QUIET
t
32
9
th
falling edge, having
THREE-
STATE