MAX146ACAP+ Maxim Integrated Products, MAX146ACAP+ Datasheet - Page 14

• Manufacturer Part Number: MAX146ACAP+
• Description: IC ADC LP 12-BIT 133KSPS 20-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX146ACAP+

• Number Of Bits: 12
• Sampling Rate (per Second): 133k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 640mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 12 bit
• Interface Type: 4-Wire (SPI, QSPI, MICROWIRE, TMS320)
• Voltage Reference: Internal 2.5 V or External
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
processor’s convenience, at any clock rate from 0MHz
to 2MHz. SSTRB goes low at the start of the conversion
and then goes high when the conversion is complete.
SSTRB is low for a maximum of 7.5µs (SHDN = FLOAT),
during which time SCLK should remain low for best
noise performance.
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the next falling clock edge produces the
MSB of the conversion at DOUT, followed by the
remaining bits in MSB-first format (Figure 9). CS does
Figure 9. Internal Clock Mode Timing
Figure 10. Internal Clock Mode SSTRB Detailed Timing
14
SSTRB
______________________________________________________________________________________
SCLK
DOUT
SSTRB
DOUT
SCLK
A/D STATE
CS
DIN
CS
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
START
1
PD0 CLOCK IN
SEL2 SEL1 SEL0
2
3
IDLE
t
CSH
4
UNI/
BIP
5
SGL/
DIF
(f
ACQUISITION
SCLK
6
1.5µs
PD1
t
SSTRB
= 2MHz)
7
PD0
8
(SHDN = FLOAT)
CONVERSION
7.5µs MAX
t
t
CONV
CONV
9
not need to be held low once a conversion is started.
Pulling CS high prevents data from being clocked into
the MAX146/MAX147 and three-states DOUT, but it
does not adversely affect an internal clock mode
conversion already in progress. When internal clock
mode is selected, SSTRB does not go into a high-
impedance state when CS goes high.
Figure 10 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX146/MAX147 at clock rates exceeding 2.0MHz
if the minimum acquisition time (t
1.5µs.
MSB B10
B11
IDLE
10
11
B9
12
t
SCK
18
B2
19
B1
20
LSB
B0
21
t
CSS
FILLED WITH
ZEROS
22
ACQ
23
24
) is kept above
t
DO