MAX1167BEEE+ Maxim Integrated Products, MAX1167BEEE+ Datasheet - Page 25

• Manufacturer Part Number: MAX1167BEEE+
• Description: IC ADC 16BIT 200KSPS 16-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1167BEEE+

• Number Of Bits: 16
• Sampling Rate (per Second): 200k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 667mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Digital noise can couple to AIN_ and REF. The conversion
clock (SCLK) and other digital signals active during input
acquisition contribute noise to the conversion result.
Noise signals, synchronous with the sampling interval,
result in an effective input offset. Asynchronous signals
produce random noise on the input, whose high-frequen-
cy components can be aliased into the frequency band
of interest. Minimize noise by presenting a low imped-
ance (at the frequencies contained in the noise signal) at
the inputs. This requires bypassing AIN_ to AGND, or
buffering the input with an amplifier that has a small-sig-
nal bandwidth of several megahertz (doing both is prefer-
able). AIN has a typical bandwidth of 4MHz.
Avoid degrading dynamic performance by choosing an
amplifier with distortion much less than the total har-
monic distortion of the MAX1167/MAX1168 at the fre-
quencies of interest (THD = -100dB at 1kHz). If the
chosen amplifier has insufficient common-mode rejec-
tion, which results in degraded THD performance, use
the inverting configuration (positive input grounded) to
eliminate errors from this source. Low-temperature-
coefficient, gain-setting resistors reduce linearity errors
caused by resistance changes due to self-heating. To
Table 8. Detailed SSPSTAT Register Contents
X = Don’t care.
Figure 21b. QSPI Interface Timing Sequence (External Clock, 8-Bit Data Transfer, CPOL = CPHA = 0)
Multichannel, 16-Bit, 200ksps Analog-to-Digital
DOUT*
*WHEN CS IS HIGH, DOUT = HIGH-Z
SCLK
SMP
CKE
R/W
D/A
CS
UA
BF
P
S
CONTROL BIT
______________________________________________________________________________________
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
1
SAMPLING INSTANT
4
SETTINGS
6
0
1
X
X
X
X
X
X
Digital Noise
Distortion
8
D15
MSB
D14
SPI Data-Input Sample Phase. Input data is sampled at the middle of
the data output time.
SPI Clock Edge-Select Bit. Data is transmitted on the rising edge of the
serial clock.
Data Address Bit
Stop Bit
Start Bit
Read/Write Bit Information
Update Address
Buffer-Full Status Bit
SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT)
D13
D12
12
reduce linearity errors due to finite amplifier gain, use
amplifier circuits with sufficient loop gain at the fre-
quencies of interest.
To improve DC accuracy, choose a buffer with an offset
much less than the MAX1167/MAX1168s’ offset (±10mV
max for +5V supply), or whose offset can be trimmed
while maintaining stability over the required temperature
range.
Figure 22a. SPI-Interface Connection for a PIC16/PIC17
D11
D10
MAX1167
MAX1168
D9
V
DD
D8
16
GND
DOUT
SCLK
CS
D7
D6
D5
D4
Converters
20
D3
D2
SCK
SDI
I/O
D1
PIC16/17
V
DC Accuracy
DD
LSB
D0
24
HIGH-Z
25