AD7997BRUZ-1 Analog Devices Inc, AD7997BRUZ-1 Datasheet - Page 29

• Manufacturer Part Number: AD7997BRUZ-1
• Description: IC ADC 10BIT 8CHAN I2C 20TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7997BRUZ-1

• Data Interface: I²C, Serial
• Operating Temperature: -40°C ~ 85°C
• Number Of Bits: 10
• Sampling Rate (per Second): 188k
• Number Of Converters: 1
• Power Dissipation (max): 2.2mW
• Voltage Supply Source: Single Supply
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 10bit
• Input Channel Type: Single Ended
• Supply Voltage Range - Analogue: 2.7V To 5.5V
• Supply Current: 1.4mA
• No. Of Pins: 20
• Sampling Rate: 188kSPS
• Rohs Compliant: Yes
• Number Of Elements: 1
• Resolution: 10Bit
• Architecture: SAR
• Sample Rate: 188KSPS
• Input Polarity: Unipolar
• Input Type: Voltage
• Rated Input Volt: 2.5V
• Differential Input: No
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 6.05mW
• Differential Linearity Error: ±0.5LSB
• Integral Nonlinearity Error: ±0.5LSB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: TSSOP
• Input Signal Type: Single-Ended
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7997CBZ - BOARD EVALUATION AD7997
• Lead Free Status / Rohs Status: Compliant

MODE 2 – COMMAND MODE
This mode allows a conversion to be automatically initiated any
time a write operation occurs. In order to use this mode, the
Command Bits C4 to C1 in the address pointer byte shown in
Table 7 must be programmed.
To select a single analog input for conversion in this mode, the
user must set Bits C4 to C1 of the address pointer byte to
indicate which channel to convert on (see Table 26). When all
four command bits are 0, this mode is not in use.
To select a sequence of channels for conversion in this mode,
first select the channels to be included in the sequence by
setting the channel bits in the configuration register. Next, set
the command bits in the address pointer byte to 0111. With the
command bits of the address pointer byte set to 0111, the ADC
knows to look in the configuration register for the sequence of
channels to be converted. The ADC starts converting on the
lowest channel in the sequence and then the next lowest until all
the channels in the sequence are converted. The ADC stops
converting the sequence when it receives a STOP bit.
Figure 29 illustrates a 2-byte read operation from the
conversion result register. This operation is preceded typically
by a write to the address pointer register so that the following
read accesses the desired register, in this case the conversion
result register (see Figure 26). If Command Bits C4 to C1 are set
when the contents of the address pointer register are being
loaded, the AD7997/AD7998 begins to power up and convert
upon the selected channel(s). Power-up begins on the fifth SCL
falling edge of the address point byte, (see point A in Figure 33).
Table 26. Address Pointer Byte
C4
0
1
1
1
1
1
1
1
1
0
C3
0
0
0
0
0
1
1
1
1
1
C2
0
0
0
1
1
0
0
1
1
1
C1
0
0
1
0
1
0
1
0
1
1
P3
0
0
0
0
0
0
0
0
0
0
P2
0
0
0
0
0
0
0
0
0
0
P1
0
0
0
0
0
0
0
0
0
0
P0
0
0
0
0
0
0
0
0
0
0
Mode 2, Convert On
Not selected
V
V
V
V
V
V
V
V
Sequence of channels selected in the
configuration register, Bits D11 to D4.
IN
IN
IN
IN
IN
IN
IN
IN
1
2
3
4
5
6
7
8
Rev. 0 | Page 29 of 32
Table 26 shows the channel selection in this mode via
Command Bits C4 to C1 in the address pointer register. The
wake-up, acquisition, and conversion times combined should
take approximately 3 µs. Following the write operation, the
AD7997/AD7998 must be addressed again to indicate that a
read operation is required. The read then takes place from the
conversion result register. This read accesses the conversion
result from the channel selected via the command bits. If
Command Bits C4 to C1 were set to 0111, and Bits D4 and D5
were set in the configuration register, a 4-byte read would be
necessary. The first read accesses the data from the conversion
on V
V
illustrates how this mode operates; the user would first have
written to the configuration register to select the sequence of
channels to be converted before write addressing the part with
the command bits set to 0111.
When operating the AD7997-1/AD7998-1 in Mode 2 with a
high speed mode, 3.4 MHz SCL, the conversion may not be
complete before the master tries to read the conversion result.
If this is the case, the AD7997-1/AD7998-1 holds the SCL line
low during the ACK clock after the read address, until the con-
version is complete. When the conversion is complete, the
AD7997-1/AD7998-1 releases the SCL line and the master can
then read the conversion result.
After the conversion is initiated by setting the command bits
in the address pointer byte, if the AD7997/AD7998 receives a
STOP or NACK from the master, the AD7997/AD7998 stops
converting.
IN
2. The second read accesses this data from V
IN
1. While this read takes place, a conversion occurs on
Comments
With the pointer Bits P3–P0 set to all 0s,
the next read accesses the results of the
conversion result register.
AD7997/AD7998
IN
2. Figure 34