CS5525-ASZ Cirrus Logic Inc, CS5525-ASZ Datasheet
CS5525-ASZ
Specifications of CS5525-ASZ
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CS5525-ASZ Summary of contents
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... Latch A2 A3 CPD http://www.cirrus.com General Description The 16-bit CS5525 and the 20-bit CS5526 are highly in- tegrated instrumentation amplifier, a PGA (programmable gain amplifier), eight digital filters, and self and system cali- bration circuitry. The converters are designed to provide their own nega- ...
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... CS5525, and LSB 16 20 Input Range, (Bipolar/Unipolar Mode 100 130 nV 130 nV 190 nV 200 nV 250 nV 300 nV 500 nV 1.0 µV 1.5 µV 2.0 µV 4.0 µV 8.0 µV 10 µV 20.0 µV 30 µ ...
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... The maximum full-scale signal can be limited by saturation of circuitry within the internal signal path. 11. All outputs unloaded. All input CMOS levels. DS202F5 (Continued) Bipolar/Unipolar Mode -0.150 (Note 5) Bipolar/Unipolar Mode (Note 9) Bipolar/Unipolar Mode (Note 10 NBV (Note 11) CS5525 CS5526 Min Typ Max Unit - 0.950 V NBV - VA+ V 1.85 - 2.65 V 0.0 ...
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... VA ±5%; VD+ = 3.0 V ±10%; GND = 0; A Symbol V IH XIN SCLK (VD XIN SCLK -400 µA out CPD -4.0 mA out SDO -5.0 mA out 400 µA out CPD out SDO 5.0 mA out out CS5525 CS5526 Min Typ Max Unit 0.6 VD 3 0.8 V 0 0.6 V (VA (VD (VD+) - 1.0 - ...
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... Positive Digital VD+ Positive Analog VA+ Negative Potential NBV (Note 16 and 17 OUT (Note 18) PDN VREF pins V INR AIN Pins V INA V IND stg CS5525 CS5526 Ratio Unit XIN/2 Hz 1/f s out Min Typ Max Unit 2.7 5.0 5.25 V 4.75 5.0 5.25 V 1.0 2.5 3.0 V -1.8 -2 ...
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... Any Digital Output (Note 20) t fall SCLK Any Digital Output (Note 21) t ost t por SCLK t 0 (Note 22) Pulse Width High t 1 Pulse Width Low CS5525 CS5526 Min Typ Max Unit 30 32.768 36 kHz 30 32.768 100 1.0 µ 100 µ 1.0 µ 100 µ ...
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... Continuous Running SCLK Timing (Not to Scale DS202F5 SDI Write Timing (Not to Scale SDO Read Timing (Not to Scale) CS5525 CS5526 ...
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... This enables the CS5525/26 to measure negative voltages with re- Figure 1. CS5525/26 Configured to use on-chip charge pump to supply NBV. 8 CS5525 CS5526 spect to ground, making the converters ideal for thermocouple temperature measurements ...
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... The CS5525/26 are optimized for the measurement of thermocouple outputs, but they are also well suited for the measurement of ratiometric bridge transducer outputs. Figure 5 CS5525/26 connected to measure the output of a ratiometric differential bridge transducer while op- erating from a single +5 V supply sim ila µ ...
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... Figure 5. CS5525/26 Configured for Single Supply Bridge Measurement. System Initialization When power to the CS5525/26 is applied, they are held in a reset condition until their 32.768 kHz os- cillators have started and their start-up counter-tim- er elapses. Due to the high 32.768 kHz crystal, the oscillators take 400-600 ms to start. The converter’ ...
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... Reading/Writing On-Chip Registers The CS5525/26’s offset, gain, and configuration registers are read/writable while the conversion data register is read only. To perform a read from a specific register, the R/W bit of the command word must be a logic 1. The SC, CC, and PS/R bits must be logic 0 and the CB (MSB) bit must be a logic 1 ...
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... Offset -- Self-Calibration 010 Gain -- Self-Calibration 011 Offset Self-Calibration followed by Gain Self-Calibration 100 Not used. 101 Offset -- System Calibration 110 Gain -- System Calibration 111 Not Used. Table 2. Configuration Register CS5525 CS5526 D16 D15 D14 D13 LPM WR2 WR1 WR0 PSS DF CC2 ...
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... clock c ycles for each convers ion except the first conv ersion w hich w ill take clock c ycles DS202F5 ( t giste rite C ycle ata ( for S et gisters ) Read C ycle tin nversion R ead ( Figure 6. Command and Data Word Timing. CS5525 CS5526 LSB LSB ata ...
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... Analog Input Figure 7 illustrates a block diagram of the analog in- put signal path inside the CS5525/26. The front end consists of a chopper-stabilized instrumentation am- plifier with 20X gain and a programmable gain sec- tion. The instrumentation amplifier is powered from VA+ and from the NBV (Negative Bias Voltage) pin allowing the CS5525/ operated in either of two analog input configurations ...
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... VREF voltage divided by the Gain Factor. See Ta- ble 3 to determine if the CS5525/26 are being used properly. For example, in the 55 mV range to de- termine the nominal input voltage to the modulator, divide VREF (2 ...
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... Voltage Reference The CS5525/26 are specified for operation with a 2.5 V reference voltage between the VREF+ and VREF- pins of the devices. For a single-ended ref- erence voltage, such as the LT1019-2.5, the refer- ence’s output is connected to the VREF+ pin of the CS5525/26 ...
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... Reading the configuration register alone will not clear the DF bit. Self Calibration The CS5525/26 offer both self offset and self gain calibrations. For the self-calibration of offset in the 25 mV, 55 mV, and 100 mv ranges, the converter internally ties the inputs of the instrumentation am- plifier together and routes them to the AIN- pin as shown in Figure 10 ...
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... Connections + Figure 14. System Calibration of Offset (High Ranges). External Connections Full Scale + - Figure 15. System Calibration of Gain (Low Ranges) External Connections + Full Scale - + CM - Figure 16. System Calibration of Gain (High Ranges). CS5525 CS5526 + AIN+ X20 - AIN- + AIN+ X20 - AIN- + AIN+ X20 - AIN- + AIN+ X20 - AIN- ...
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... Note: The shift operators are used here to align the decimal points of words of various lengths. Data to the right of the decimal point may be used in the calculations shown. For the CS5525 all conversion results (Ru, Rc...) are 16 bits instead DS202F5 of 20 bits. To get the equations to work correctly pad the 16 bit results with four zeros (on the right) ...
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... VA+, hence, their output voltage for a logic 1 will be limited to the VA+ voltage. Serial Port Interface The CS5525/26 serial interface consist of four pins, SCLK, SDO, SDI, and CS. The CS pin must be held low (logic 0) before SCLK transitions can be recognized by the port logic. The SDO output will be held at high impedance any time logic 1 ...
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... Upon reset the converters are set to operate with an output word rate of 15.0 Sps. Clock Generator The CS5525/26 include a gate which can be con- nected with an external crystal to provide the master clock for the chips. They are designed to operate us- ing a low-cost 32.768 kHz “tuning fork” type crys- tal ...
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... Output Word Rate = 1) first followed by the rest of the data bits in descend- ing order. For the CS5525 the last byte is composed of bits D7-D4, which are always logic 1; D3-D2, which are always logic 0; and bits D1-D0 which are the two flag bits. For the CS5526 the last byte in- cludes data bits D7-D4, D3-D2 which are always logic 0 and the two flag bits ...
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... PCB Layout The CS5525/26 should be placed entirely over an an- alog ground plane with both the AGND and DGND pins of the device connected to the analog plane. Place the analog-digital plane split immediately adja- cent to the digital portion of the chip ...
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... VREF- VOLTAGE REFERENCE INPUT 3 18 AIN+ CS CHIP SELECT 4 17 AIN- SDI SERIAL DATA INPUT 5 16 NBV A3 LOGIC OUTPUT LOGIC OUTPUT SDO SERIAL DATA OUTPUT 8 13 CPD VD+ POSITIVE DIGITAL POWER 9 12 XIN DGND DIGITAL GROUND 10 11 XOUT SCLK SERIAL CLOCK INPUT CS5525 CS5526 DS202F5 ...
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... Square wave output used to provide energy for the charge pump. Power Supply Connections VA+ - Positive Analog Power, Pin 2. Positive analog supply voltage. Nominally +5 V. VD+ - Positive Digital Power, Pin 13. Positive digital supply voltage. Nominally +3 AGND - Analog Ground, Pin 1. Analog Ground. DGND - Digital Ground, Pin 12. Digital Ground. DS202F5 CS5525 CS5526 25 ...
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... AIN- pin.). When in unipolar mode (U/B bit = 1). Units are in LSBs. Bipolar Offset The deviation of the mid-scale transition(111...111 to 000...000) from the ideal (1/2 LSB below the voltage on the AIN- pin). When in bipolar mode (U/B bit = 0). Units are in LSBs. 26 CS5525 CS5526 DS202F5 ...
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... CS5525 CS5526 ∝ SIDE VIEW MILLIMETERS MAX 4.57 1.02 0.56 1.65 0.38 26.42 6.60 2.67 8.25 3.81 0° 15° 27 ...
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... CS5525 CS5526 1 E1 END VIEW L NOTE MILLIMETERS MAX -- 2.13 0.25 1.88 0.38 2,3 7.50 1 8.20 5.60 1 0.69 1.03 8° ...
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... CS5525-AS CS5525-ASZ (Lead Free) CS5526-BP CS5526-BS CS5526-BSZ (Lead Free) ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5525-AS CS5525-ASZ (Lead Free) CS5526-BP CS5526-BS CS5526-BSZ (Lead Free) * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. DS202F5 Package 20-pin SSOP 20-pin Plastic Dip (0.300”) ...
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... Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. 30 CS5525 CS5526 Changes DS202F5 ...