AD7194BCPZ Analog Devices Inc, AD7194BCPZ Datasheet
AD7194BCPZ
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AD7194BRUZ
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AD7194BCPZ Summary of contents
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FEATURES Fast settling filter option 8 differential/16 pseudo differential input channels RMS noise 4.7 Hz (gain = 128) 15.5 noise-free bits at 2.4 kHz (gain = 128 noise-free bits (gain = 1) Offset drift: ...
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AD7194 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ................................................................ 7 Absolute Maximum Ratings ............................................................ 9 Thermal Resistance ...................................................................... 9 ESD ...
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SPECIFICATIONS 5. 2 5.25 V, AGND = DGND = 0 V; REFINx(+) = +2 MCLK = 4.92 MHz unless ...
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AD7194 Parameter Min 2 Normal Mode Rejection 4 Sinc Filter Internal Clock @ 50 Hz 100 External Clock @ 50 Hz 120 120 ...
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Parameter Min REFERENCE INPUT REFIN Voltage 1 Absolute REFIN Voltage AGND − 0.05 2 Limits Average Reference Input Current Average Reference Input Current Drift 2 Normal Mode Rejection Common-Mode Rejection Reference Detect Levels 0.3 TEMPERATURE SENSOR Accuracy Sensitivity BURNOUT CURRENTS ...
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AD7194 Parameter Min 2 SYSTEM CALIBRATION Full-Scale Calibration Limit Zero-Scale Calibration −1.05 × FS Limit Input Span 0.8 × POWER REQUIREMENTS Power Supply Voltage AV − AGND − DGND 2.7 DD Power Supply Currents AI ...
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TIMING CHARACTERISTICS 5. 2 5.25 V, AGND = DGND = 0 V, Input Logic Input Logic Table 2. Parameter Limit at T ...
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AD7194 Circuit and Timing Diagrams DOUT/RDY (O) SCLK (I) I (1.6mA WITH DV SINK 100µA WITH OUTPUT 1.6V PIN 50pF I (200µA WITH DV SOURCE 100µA WITH DV DD Figure 2. Load Circuit for Timing Characterization CS ...
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ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter AV to AGND DD to AGND DV DD AGND to DGND Analog Input Voltage to AGND Reference Input Voltage to AGND Digital Input Voltage to DGND Digital ...
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AD7194 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 AIN1/P3 Analog Input/Digital Output Pin. This pin can function as an analog input pin. When the GP32EN bit is set to 1, the pin ...
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Pin No. Mnemonic Description 23 AV Analog Supply Voltage 5. with Digital Supply Voltage with DV 25 SYNC Logic input that allows for synchronization ...
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AD7194 TYPICAL PERFORMANCE CHARACTERISTICS 8,387,952 8,387,950 8,387,948 8,387,946 8,387,944 8,387,942 8,387,940 8,387,938 8,387,936 8,387,934 0 200 400 600 SAMPLE Figure 6. Noise ( Output Data Rate = 4.7 Hz, REF DD Gain = 128, Chop ...
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V (V) IN Figure 12. INL (Gain = –5 –10 –15 –20 –0.03 –0.02 –0.01 0 0.01 V (V) ...
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AD7194 GAIN = 1 GAIN = 8 16 GAIN = 16 GAIN = 32 GAIN = 64 GAIN = 128 100 OUTPUT DATA RATE (Hz) 4 Figure 18. Noise-Free Resolution (Sinc Filter, Chop ...
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RMS NOISE AND RESOLUTION The following tables show the rms noise, peak-to-peak noise, effective resolution, and noise-free (peak-to-peak) resolution of the AD7194 for various output data rates and gain settings with 4 3 chop disabled for the sinc and sinc ...
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AD7194 3 SINC CHOP DISABLED Table 9. RMS Noise (nV) vs. Gain and Output Data Rate Output Data Filter Word (Decimal) Rate (Hz) 1023 4.7 640 7.5 480 150 16 300 5 960 2 ...
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FAST SETTLING Table 12. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word Output Data (Decimal) Average Rate ( 42. 50. 126. 252.63 Table ...
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AD7194 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers that are described on the following pages wherein the term, set, implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise ...
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COMMUNICATIONS REGISTER RS2, RS1, RS0 = 000 The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register. The data written to the communi- cations register determine whether ...
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AD7194 STATUS REGISTER RS2, RS1, RS0 = 000; Power-On/Reset = 0x80 The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation ...
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MODE REGISTER RS2, RS1, RS0 = 001; Power-On/Reset = 0x080060 The mode register is a 24-bit register from which data can be read or to which data can be written. This register is used to select the operating mode, the ...
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AD7194 Bit Location Bit Name Description MR12 CLK_DIV Clock divide-by-2. When CLK_DIV is set, the master clock is divided by 2. For normal conversions, set this bit to 0. When performing internal full-scale calibrations, this bit must be set when ...
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Table 20. Operating Modes (MD) MD2 MD1 MD0 Mode Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. The DOUT/RDY pin and the RDY bit ...
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AD7194 CONFIGURATION REGISTER RS2, RS1, RS0 = 010; Power-On/Reset = 0x000117 The configuration register is a 24-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for ...
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Table 21. Configuration Register Bit Designations Bit Location Bit Name Description CON23 Chop Chop enable bit. When the chop bit is cleared, chop is disabled. With chop disabled, higher conversion rates are allowed. For an FS word of 96 decimal ...
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AD7194 Channel Selection (Pseudo Bit = 0) Table 22. Positive Input Selection Positive Input Enable Bits in Positive the Configuration Register Input Enabled CH7 CH6 CH5 CH4 AIN(+) AIN1 AIN2 0 0 ...
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DATA REGISTER RS2, RS1, RS0 = 011; Power-On/Reset = 0x000000 The conversion result from the ADC is stored in this data register. This is a read-only, 24-bit register. Upon completion of a read operation from this register, the RDY pin/bit ...
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AD7194 OFFSET REGISTER RS2, RS1, RS0 = 110; Power-On/Reset = 0x800000) The offset register holds the offset calibration coefficient for the ADC. The power-on reset value of the offset register is 0x800000. The register is a 24-bit read/write register. It ...
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ADC CIRCUIT INFORMATION AIN1/P3 AIN2/P2 AIN3/P1/REFIN2(+) AIN4/P0/REFIN2(–) AIN5 AIN16 AINCOM OVERVIEW The AD7194 is an ultralow noise ADC that incorporates a sigma-delta (Σ-Δ) modulator, a buffer, PGA, and on-chip digital filtering intended for the measurement of wide dynamic range signals ...
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AD7194 ANALOG INPUT CHANNEL The AD7194 uses flexible multiplexing so any of the analog input pins AIN1 to AIN16 can be selected as a positive input or a negative input (see Table 22 and Table 23). The AINCOM pin can ...
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External decoupling on the REFINx pins is not recommended in this type of circuit configuration. Conversely, if large decoupling capacitors are used on the reference inputs, there should be no resistors in series with the reference inputs. Recommended 2.5 ...
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AD7194 absolute input voltage range specifications when the analog inputs are buffered and chop is disabled. DIGITAL INTERFACE As indicated in the On-Chip Registers section, the program- mable functions of the AD7194 are controlled using a set of on-chip registers. ...
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Single Conversion Mode In single conversion mode, the AD7194 is placed in power- down mode after conversions. When a single conversion is initiated by setting MD2 to 0, MD1 to 0, and MD0 the mode register, the ...
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AD7194 Continuous Conversion Mode Continuous conversion is the default power-up mode. The AD7194 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete low, the DOUT/ RDY line also ...
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Continuous Read Rather than write to the communications register each time a conversion is complete to access the data, the AD7194 can be configured so that the conversions are placed on the DOUT/ RDY line automatically. By writing 01011100 to ...
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AD7194 RESET The circuitry and serial interface of the AD7194 can be reset by writing consecutive 1s to the device; 40 consecutive 1s are required to perform the reset. This resets the logic, the digital filter, and the analog modulator, ...
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Following the one-point calibration, the internal temperature sensor has an accuracy of ±2°C, typically. LOGIC OUTPUTS The AD7194 has four general-purpose digital outputs: P0, P1, P2, and P3. These are enabled using the GP32EN and GP10EN bits in the GPOCON ...
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AD7194 An internal zero-scale calibration, system zero-scale calibration, and system full-scale calibration can be performed at any output data rate. An internal full-scale calibration can be performed at any output data rate for which the filter word, FS[9:0], is divisible ...
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DIGITAL FILTER The AD7194 offers a lot of flexibility in the digital filter. The device has five filter options. The device can be operated with sinc or sinc filter, chop can be enabled or disabled, and zero ...
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AD7194 When the analog input is constant or a channel change occurs, valid conversions are available at a constant output data rate. When conversions are being performed on a single channel and a step change occurs on the analog input, ...
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The output data rate when zero latency is disabled and 12.5 Hz when zero latency is enabled. Figure 34 shows the 4 frequency response of the sinc filter. The filter provides 50 Hz ±1 Hz and 60 ...
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AD7194 The output data rate equals /(3 × 1024 × FS[9:0]) ADC SETTLE CLK where the output data rate. ADC f is the master clock (4.92 MHz nominal). CLK FS[9:0] is the decimal ...
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Simultaneous 50 Hz and 60 Hz rejection is obtained when FS[9:0] is set to 480 (master clock = 4.92 MHz), as shown in Figure 41. The output data rate when zero latency is disabled and 3.3 Hz ...
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AD7194 When a channel change occurs, the modulator and filter reset. The complete settling time is required to generate the first conversion after the channel change. Subsequent conversions on this channel occur at 1/f . ADC CHANNEL A CHANNEL CONVERSIONS ...
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CHOP ENABLED (SINC FILTER) With chop enabled, the ADC offset and offset drift are minimized. The analog input pins are continuously swapped. With the analog input pins connected in one direction, the settling time of the sinc filter is ...
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AD7194 The 50 Hz/60 Hz rejection can be improved by setting the REJ60 bit in the mode register to 1. With FS[9:0] set to 96 and REJ60 set to 1, the filter response shown in Figure 52 is achieved. The ...
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Hz when the master clock equals 4.92 MHz. The sinc filter places the first notch /(1024 × FS[9:0]) NOTCH CLK The postfiltering places notches at f NOTCH amount of averaging) and multiples of this ...
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AD7194 3 FAST SETTLING MODE (SINC FILTER) In fast settling mode, the settling time is close to the inverse of the first filter notch. Therefore, the user can achieve 50 Hz and/ rejection at an output data rate ...
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FREQUENCY (Hz) Figure 63. Filter Response for Average + Decimate Filter 3 (Sinc Filter, FS[9: Average by 16) Figure 64 shows ...
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AD7194 FAST SETTLING MODE (CHOP ENABLED) Chop can be enabled in the fast settling mode. With chop enabled, the ADC offset and offset drift are minimized. The analog input pins are continuously swapped. With the analog input pins connected in ...
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SUMMARY OF FILTER OPTIONS The AD7194 has several filter options. The filter that is chosen affects the output data rate, settling time, the rms noise, the stop band attenuation, and the 50 Hz/60 Hz rejection. 1 Table 36. Filter Summary ...
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AD7194 GROUNDING AND LAYOUT Because the analog inputs and reference inputs are differential, most of the voltages in the analog modulator are common- mode voltages. The high common-mode rejection of the part removes common-mode noise on these inputs. The analog ...
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APPLICATIONS INFORMATION The AD7194 provides a low cost, high resolution analog-to- digital function. Because the analog-to-digital function is provided by a Σ-Δ architecture, the part is more immune to noisy environments, making it ideal for use in sensor measurement and ...
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... PIN 1 INDICATOR 0.80 0.75 0.70 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 AD7194BCPZ −40°C to +105°C 1 AD7194BCPZ-REEL −40°C to +105°C 1 AD7194BCPZ-REEL7 −40°C to +105° RoHS Compliant Part. 5.10 0.30 5.00 SQ 0.25 4.90 0. 0.50 BSC 17 16 0.50 TOP VIEW BOTTOM VIEW 0 ...
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NOTES Rev Page AD7194 ...
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AD7194 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. registered trademarks are the property of their respective owners. D08566-0-10/09(0) Rev. ...