AD9258BCPZ-125 Analog Devices Inc, AD9258BCPZ-125 Datasheet - Page 13

• Manufacturer Part Number: AD9258BCPZ-125
• Description: IC ADC 14BIT 125MSPS DL 64LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9258BCPZ-125

• Data Interface: Serial
• Design Resources: High Performance, Dual Channel IF Sampling Receiver (CN0140)
• Number Of Bits: 14
• Sampling Rate (per Second): 125M
• Number Of Converters: 2
• Power Dissipation (max): 788mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Resolution (bits): 14bit
• Sampling Rate: 125MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Supply Voltage Range - Digital: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Descriptions (Parallel CMOS Mode)
Pin No.
ADC Power Supplies
10, 19, 28, 37
49, 50, 53, 54, 59,
60, 63, 64
4, 5, 25, 26
0
ADC Analog
51
52
62
61
55
56
58
57
1
2
Digital Input
3
Digital Outputs
27
29
30
31
Mnemonic
DRVDD
AVDD
NC
AGND,
Exposed Pad
VIN+A
VIN−A
VIN+B
VIN−B
VREF
SENSE
RBIAS
VCM
CLK+
CLK−
SYNC
D0A (LSB)
D1A
D2A
D3A
D0B (LSB)
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE
PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED
PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
DRVDD
SYNC
CLK+
CLK–
Input
Type
Supply
Supply
Ground
Input
Input
Input
Input
Input/Output
Input
Input/Output
Output
Input
Input
Output
Output
Output
Output
D1B
D2B
D3B
D4B
D5B
D6B
D7B
D8B
D9B
NC
NC
Figure 6. LFCSP Parallel CMOS Pin Configuration (Top View)
10
12
13
14
15
16
11
1
2
3
4
5
6
7
8
9
PIN 1
INDICATOR
Description
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Do Not Connect.
The exposed thermal pad on the bottom of the package provides the analog
ground for the part. This exposed pad must be connected to ground for proper
operation.
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select. See Table 11 for details.
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
Digital Synchronization Pin. Slave mode only.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Rev. A | Page 13 of 44
PARALLEL CMOS
(Not to Scale)
AD9258
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PDWN
OEB
CSB
SCLK/DFS
SDIO/DCS
ORA
D13A (MSB)
D12A
D11A
D10A
D9A
DRVDD
D8A
D7A
D6A
D5A
AD9258