MAX1415EWE+ Maxim Integrated Products, MAX1415EWE+ Datasheet - Page 27

• Manufacturer Part Number: MAX1415EWE+
• Description: IC ADC 16BIT DELTA SIGMA 16-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MAX1415EWE+

• Number Of Bits: 16
• Sampling Rate (per Second): 500
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 762mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -45°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Set CLK = 0 if the external clock frequency is 1MHz
with CLKDIV = 0 or 2MHz with CLKDIV = 1.
FS1, FS0: (Default = 0, 1) Filter-Selection Bits. These bits,
in addition to the CLK bit, determine the output data rate
and the digital filter cutoff frequency. See
FS1 and FS0 settings. Recalibrate when the filter charac-
teristics are changed.
The data register is a 16-bit read-only register. Figure 9
shows how to read conversion results using the
data register.
The data from the data register is read through DOUT.
DOUT changes on the falling edge of SCLK and is valid
on the rising edge of SCLK. The data-register format is
16-bit straight binary for unipolar mode with zero scale
equal to 0x0000, and offset binary for bipolar mode
with zero scale equal to 0x1000.
Table 12. Clock Register
Table 13. Output Data Rate and Notch Frequency vs. Filter Select and CLKIN Frequency
*These values are given for CLKDIV = 0. External-clock frequency, f CLKIN , equals two times the values in this column if CLKDIV = 1.
**The filter -3dB filter cutoff frequency = 0.262 x filter first notch frequency.
Name
Defaults
FUNCTION
CLKIN FREQUENCY
f
CLKIN
2.4576
2.4576
2.4576
2.4576
1
1
1
1
(MHz)*
(MSB)
MXID
______________________________________________________________________________________
RESERVED
1
ZERO
0
CLK
0
0
0
0
1
1
1
1
CLOCK ENABLE
INTERNAL
INTCLK
Data Register
0
FS1
Table 13 for
16-Bit, Low-Power, 2-Channel,
0
0
1
1
0
0
1
1
DISABLE
FS0
CLOCK
CLKDIS
0
1
0
1
0
1
0
1
0
This register is reserved for factory testing of the
device. For proper operation of the MAX1415/
MAX1416, do not change this register from its default
power-on reset values.
The MAX1415/MAX1416 contain one offset register and
one gain register for each input channel. Each register
is 24 bits wide and can be written and read. The offset
registers store the calibration coefficients resulting from
a zero-scale calibration, and the gain registers store
the calibration coefficients resulting from a full-scale
calibration. The data stored in these registers are 24-bit
straight binary values representing the offset or gain
errors associated with the selected channel. A 24-bit
read or write operation can be performed on the cali-
bration registers for any selected channel. During a
write operation, 24 bits of data must be written to the
register, or no data is transferred.
OUTPUT DATA RATE
(FIRST NOTCH) (Hz)
DIVIDER
CLOCK
CLKDIV
Sigma-Delta ADCs
0
100
200
250
500
20
25
50
60
Offset and Gain-Calibration Registers
SELECT
CLOCK
CLK
1
-3dB FILTER CUTOFF**
FILTER SELECT
FS1
(Hz)
5.24
6.55
26.2
52.4
13.1
15.7
65.5
Test Register
131
0
FS0
(LSB)
1
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