MAX1146BCUP+ Maxim Integrated Products, MAX1146BCUP+ Datasheet - Page 18

IC ADC 14BIT 116KSPS 20-TSSOP

MAX1146BCUP+

Manufacturer Part Number
MAX1146BCUP+
Description
IC ADC 14BIT 116KSPS 20-TSSOP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX1146BCUP+

Number Of Bits
14
Sampling Rate (per Second)
116k
Data Interface
MICROWIRE™, QSPI™, Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
879mW
Voltage Supply Source
Single Supply
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Multichannel, True-Differential,
Serial, 14-Bit ADCs
Figure 11. Internal Clock Mode— 18 Clocks/Conversion Timing
The MAX1146–MAX1149 provide a hardware shutdown
and two software power-down modes.
Pulling SHDN low places the converter in hardware
shutdown. The conversion is immediately terminated
and the supply current is reduced to 300nA. Allow 2ms
for the device to power-up when the internal reference
buffer is used with C
2.2µF. Larger capacitors on C
increase the power-up time (Table 6). No wake-up time
is needed for the device to power-up from fast power-
down when using an external reference.
Select a software power-down mode through the PD1
and PD0 bits of the control byte (Table 1). When the
conversion in progress is complete, software power-
down is initiated. The serial interface remains active
and the last conversion result can be clocked out. In
full power-down mode, only the serial interface remains
operational and the supply current is reduced to
300nA. In fast power-down mode, only the bandgap
reference and the serial interface remain operational,
and the supply current is reduced to 600µA.
Table 6. Internal Reference Buffer Power-
Up Times vs. Bypass Capacitors
*Power-up times are dominated by C
18
C
REFADJ
0.01µF
0.1µF
INPUT MUX
INPUT T/H
______________________________________________________________________________________
SSTRB
DOUT
SCLK
DIN
CS
*
SET ACCORDING TO PREVIOUS
CONTROL BYTE
HIGH-Z
Shutdown and Power-Down Modes
START SEL2 SEL1 SEL0
C
4.7µF
10µF
1
REF
REFADJ
TRACK
CB1
SGL/DIFUNI/BIP
POWER-UP TIMES FROM AN
EXTENDED POWER-DOWN
SET TO CB1
REFADJ
= 0.01µF and C
t
PD1
ACQ
REFADJ
PD0
8
.
25ms
2ms
t
OPEN
HOLD
CONV
and C
1
RESET TO CB1
REF
D13 D12
REF
=
4
10
START SEL2 SEL1 SEL0
D5
11
The MAX1146–MAX1149 automatically wake up from
software power-down when they receive the control
byte’s start bit (Table 1). Allow 2ms for the device to
power-up when the internal reference buffer is used
with C
capacitors on C
up time (Table 6). No wake-up time is needed for the
device to power-up from fast power-down when using
an external reference.
The MAX1146–MAX1149 can be used with an internal
or external reference voltage. The reference voltage
determines the ADC input range. The reference deter-
mines the full-scale output value (Table 7).
The MAX1146–MAX1149 contain an internal 1.250V
bandgap reference. This bandgap reference is connect-
ed to REFADJ through a 20kΩ resistor. Bypass REFADJ
with a 0.01µF capacitor to AGND. The MAX1146/
MAX1148 reference buffer has a 3.277V/V gain to pro-
vide +4.096V at REF. The MAX1147/MAX1149 reference
buffer has a 2.000V/V gain to provide +2.500V at REF.
Bypass REF with a minimum 2.2µF capacitor to AGND
when using the internal reference.
An external reference can be applied to the
MAX1146–MAX1149 in two ways:
1) Disable the internal reference buffer by connecting
2) Utilize the internal reference buffer by applying an
D4
TRACK
REFADJ to V
REF (Figure 12).
external reference to REFADJ (Figure 13).
D3
REFADJ
D2
CB2
SGL/DIF UNI/BIP
D1
D0
SET TO CB2
t
ACQ
PD1
= 0.01µF and C
REFADJ
DD
PD0
18
and apply the external reference to
HOLD
t
OPEN
CONV
and C
1
RESET TO CB2
REF
TRACK
Reference Voltage
D13 D12
REF
increase the power-
External Reference
Internal Reference
4
= 2.2µF. Larger
10
START
D5
11
SEL2
D4

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