LTC2433-1CMS#TR Linear Technology, LTC2433-1CMS#TR Datasheet - Page 16

• Manufacturer Part Number: LTC2433-1CMS#TR
• Description: IC CONV A/D 16BIT DIFF 10-MSOP
• Manufacturer: Linear Technology

Specifications of LTC2433-1CMS#TR

• Number Of Bits: 16
• Sampling Rate (per Second): 6.8
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC2433-1
APPLICATIO S I FOR ATIO
and the device begins outputting data at time t
the falling edge of CS (if EOC = 0) or t
LOW (if CS is LOW during the falling edge of EOC). The
value of t
oscillator (F
oscillator of frequency f
CS is pulled HIGH before time t
to the sleep state and the conversion result is held in the
internal static shift register.
If CS remains LOW longer than t
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle concludes
after the 19th rising edge. Data is shifted out the SDO pin
on each falling edge of SCK. The internally generated serial
clock is output to the SCK pin. This signal may be used to
shift the conversion result into external circuitry. EOC can
be latched on the first rising edge of SCK and the last bit
of the conversion result on the 19th rising edge of SCK.
After the 19th rising edge, SDO goes HIGH (EOC = 1), SCK
stays HIGH and a new conversion starts.
16
(INTERNAL)
SDO
SCK
CS
EOCtest
0
CONVERSION
= logic LOW). If F
Hi-Z
is 23 s if the device is using its internal
U
SLEEP
EOSC
(OPTIONAL)
U
TEST EOC
, then t
SLEEP
EOCtest
Hi-Z
O
<t
EOCtest
is driven by an external
EOCtest
W
Figure 9. Internal Serial Clock, Single Cycle Operation
EOCtest
EOCtest
BIT 18
EOC
, the device returns
, the first rising
after EOC goes
is 3.6/f
BIT 17
ANALOG INPUT RANGE
“O”
–0.5V
EOCtest
U
REF
REFERENCE
0.1V TO V
TO 0.5V
BIT 16
EOSC
VOLTAGE
SIG
1 F
after
2.7V TO 5.5V
REF
CC
. If
BIT 15
MSB
1
2
3
4
5
6
V
REF
REF
IN
IN
GND
CC
LTC2433-1
+
–
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 19th rising edge of
SCK, see Figure 10. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for aborting an invalid
conversion cycle, or synchronizing the start of a conver-
sion. If CS is pulled HIGH while the converter is driving
SCK LOW, the internal pull-up is not available to restore
SCK to a logic HIGH state. This will cause the device to exit
the internal serial clock mode on the next falling edge of
CS. This can be avoided by adding an external 10k pull-up
resistor to the SCK pin or by never pulling CS HIGH when
SCK is LOW.
Whenever SCK is LOW, the LTC2433-1’s internal pull-up
at pin SCK is disabled. Normally, SCK is not externally
driven if the device is in the internal SCK timing mode.
However, certain applications may require an external
driver on SCK. If this driver goes Hi-Z after outputting a
LOW signal, the LTC2433-1’s internal pull-up remains
+
–
BIT 14
SDO
SCK
DATA OUTPUT
CS
F
O
10
9
8
7
BIT 13
3-WIRE
SPI INTERFACE
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
BIT 2
BIT 1
V
CC
10k
BIT 0
LSB
CONVERSION
Hi-Z
TEST EOC
24331 F09
Hi-Z
24331fa