LTC2433-1CMS#PBF Linear Technology, LTC2433-1CMS#PBF Datasheet - Page 12

• Manufacturer Part Number: LTC2433-1CMS#PBF
• Description: IC ADC DIFF 16BIT 3WIRE 10-MSOP
• Manufacturer: Linear Technology

Specifications of LTC2433-1CMS#PBF

• Number Of Bits: 16
• Sampling Rate (per Second): 6.8
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
LTC2433-1
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
outside specifications but the following conversions will
not be affected. If the change occurs during the data output
state and the converter is in the Internal SCK mode, the
serial clock duty cycle may be affected but the serial data
stream will remain valid.
Table 3 summarizes the duration of each state and the
achievable output data rate as a function of F
SERIAL INTERFACE PINS
The LTC2433-1 transmits the conversion results and
receives the start of conversion command through a
synchronous 3-wire interface. During the conversion and
sleep states, this interface can be used to assess the
converter status and during the data output state it is used
to read the conversion result.
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 9) is used to
synchronize the data transfer. Each bit of data is shifted out
the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2433-1 creates its own serial clock by
Table 3. LTC2433-1 State Duration
State
CONVERT
SLEEP
DATA OUTPUT
12
Operating Mode
Internal Oscillator
External Oscillator
Internal Serial Clock
External Serial Clock with
Frequency f
U
U
SCK
kHz
W
F
Simultaneous 50Hz/60Hz Rejection
F
with Frequency f
(f
F
(Internal Oscillator)
F
Frequency f
O
O
O
O
EOSC
= LOW
= External Oscillator
= LOW
= External Oscillator with
O
U
.
/2560 Rejection)
EOSC
EOSC
kHz
kHz
dividing the internal conversion clock by 8. In the External
SCK mode of operation, the SCK pin is used as input. The
internal or external SCK mode is selected on power-up and
then reselected every time a HIGH-to-LOW transition is
detected at the CS pin. If SCK is HIGH or floating at power-
up or during this transition, the converter enters the inter-
nal SCK mode. If SCK is LOW at power-up or during this
transition, the converter enters the external SCK mode.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 8), provides the result
of the last conversion as a serial bit stream (MSB first)
during the data output state. In addition, the SDO pin is
used as an end of conversion indicator during the conver-
sion and sleep states.
When CS (Pin 7) is HIGH, the SDO driver is switched to a
high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW.
Chip Select Input (CS)
The active LOW chip select, CS (Pin 7), is used to test the
conversion status and to enable the data output transfer as
described in the previous sections.
Duration
147ms, Output Data Rate 6.8 Readings/s
20510/f
As Long As CS = HIGH Until CS = LOW and SCK
As Long As CS = LOW But Not Longer Than 1.09ms
(19 SCK cycles)
As Long As CS = LOW But Not Longer Than 152/f
(19 SCK cycles)
As Long As CS = LOW But Not Longer Than 19/f
(19 SCK cycles)
EOSC
s, Output Data Rate f
EOSC
/20510 Readings/s
SCK
EOSC
ms
ms
24331fa