AD7810YNZ Analog Devices Inc, AD7810YNZ Datasheet - Page 6

• Manufacturer Part Number: AD7810YNZ
• Description: IC ADC 10BIT SRL HS LP 8DIP
• Manufacturer: Analog Devices Inc

Specifications of AD7810YNZ

• Data Interface: Serial
• Number Of Bits: 10
• Sampling Rate (per Second): 350k
• Number Of Converters: 1
• Power Dissipation (max): 17.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Resolution (bits): 10bit
• Sampling Rate: 350kSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Analog: 2.7V To 5.5V
• Supply Current: 3.5mA
• Digital Ic Case Style: DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7810
CIRCUIT DESCRIPTION
Converter Operation
The AD7810 is a successive approximation analog-to-digital
converter based around a charge redistribution DAC. The ADC
can convert analog input signals in the range 0 V to V
ures 4 and 5 below show simplified schematics of the ADC.
Figure 4 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in Position A; the comparator is held in a
balanced condition; and the sampling capacitor acquires the
signal on V
When the ADC starts a conversion (see Figure 5), SW2 will
open and SW1 will move to Position B, causing the comparator
to become unbalanced. The control logic and the charge redis-
tribution DAC are used to add and subtract fixed amounts of
charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is rebal-
anced, the conversion is complete. The control logic generates
the ADC output code. Figure 11 shows the ADC transfer function.
TYPICAL CONNECTION DIAGRAM
Figure 6 shows a typical connection diagram for the AD7810. The
serial interface is implemented using two wires; the rising edge
of CONVST enables the serial interface—see Serial Interface
section for more details. V
V
V
mode, i.e., power-down. A rising edge on the CONVST input
will cause the part to power up—see Operating Modes. If power
consumption is of concern, the automatic power-down at the
end of a conversion should be used to improve power perfor-
mance. See Power vs. Throughput Rate section of the data sheet.
DD
DD
V
V
V
V
IN
IN
IN
IN
pin to provide an analog input range of 0 V to V
is first connected, the AD7810 powers up in a low current
+
+
–
–
SW1
SW1
IN+
A
A
B
B
.
Figure 5. ADC Conversion Phase
Figure 4. ADC Acquisition Phase
ACQUISITION
CONVERSION
CAPACITOR
CAPACITOR
SAMPLING
SAMPLING
PHASE
PHASE
V
V
DD
DD
/3
/3
REF
is connected to a well decoupled
SW2
SW2
COMPARATOR
COMPARATOR
REDISTRIBUTION
REDISTRIBUTION
CHARGE
CHARGE
CONTROL
CONTROL
DD
DAC
CLOCK
CLOCK
DAC
LOGIC
DD
LOGIC
OSC
OSC
. When
. Fig-
–6–
Analog Input
Figure 7 shows an equivalent circuit of the analog input struc-
ture of the AD7810. The two diodes, D1 and D2, provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by
more than 200 mV. This will cause these diodes to become
forward biased and start conducting current into the substrate.
The maximum current these diodes can conduct without caus-
ing irreversible damage to the part is 20 mA. The capacitor C2
is typically about 4 pF and can be primarily attributed to pin
capacitance. The resistor R1 is a lumped component made up of
the on resistance of a multiplexer and a switch. This resistor is
typically about 125 Ω. The capacitor C1 is the ADC sampling
capacitor and has a capacitance of 3.5 pF.
The analog input of the AD7810 is made up of a pseudo differ-
ential pair. V
signal is applied to V
the sampling capacitor is connected to V
(see Figure 8). This input scheme can be used to remove offsets
that exist in a system. For example, if a system had an offset of
0.5 V, the offset could be applied to V
to V
It is only possible to offset the input span when the reference
voltage (V
V
IN
(+)
2.7V TO 5.5V
IN+
0V TO V
V
V
IN
SUPPLY
. This has the effect of offsetting the input span by 0.5 V.
OFFSET
+
Figure 8. Pseudo Differential Input Scheme
INPUT
V
Figure 7. Equivalent Analog Input Circuit
OFFSET
REF
REF
Figure 6. Typical Connection Diagram
IN+
) is less than V
4pF
V
V
C2
IN
IN
pseudo differential with respect to V
+
–
10 F
IN+
V
AGND
V
V
, but in the pseudo differential scheme
DD
IN
IN
CONVERSION
+
–
D2
D1
0.1 F
CAPACITOR
SAMPLING
CONVERT PHASE – SWITCH OPEN
ACQUISITION PHASE – SWITCH CLOSED
PHASE
DD
V
DD
V
– V
AD7810
DD
/3
OFFSET
V
REF
125
IN–
R1
SW2
CONVST
IN–
.
SCLK
and the signal applied
D
COMPARATOR
OUT
during conversion
3.5pF
TWO WIRE
SERIAL
INTERFACE
C1
REDISTRIBUTION
IN–
CHARGE
V
DAC
DD
CONTROL
. The
CLOCK
LOGIC
REV. B
/3
OSC
C/ P