AD7927BRUZ Analog Devices Inc, AD7927BRUZ Datasheet - Page 8

IC ADC 12BIT 8CH 200KSPS 20TSSOP

AD7927BRUZ

Manufacturer Part Number
AD7927BRUZ
Description
IC ADC 12BIT 8CH 200KSPS 20TSSOP
Manufacturer
Analog Devices Inc
Datasheets

Specifications of AD7927BRUZ

Data Interface
DSP, MICROWIRE™, QSPI™, Serial, SPI™
Number Of Bits
12
Sampling Rate (per Second)
200k
Number Of Converters
1
Power Dissipation (max)
7.5mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP (0.173", 4.40mm Width)
Resolution (bits)
12bit
Sampling Rate
200kSPS
Input Channel Type
Single Ended
Supply Voltage Range - Analog
2.7V To 5.25V
Supply Current
1.5mA
Number Of Elements
1
Resolution
12Bit
Architecture
SAR
Sample Rate
200KSPS
Input Polarity
Unipolar
Input Type
Voltage
Rated Input Volt
2.5/5V
Differential Input
No
Power Supply Requirement
Analog and Digital
Single Supply Voltage (typ)
3/5V
Single Supply Voltage (min)
2.7V
Single Supply Voltage (max)
5.25V
Dual Supply Voltage (typ)
Not RequiredV
Dual Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Power Dissipation
7.5mW
Differential Linearity Error
-0.9LSB/1.5LSB
Integral Nonlinearity Error
±1LSB
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
20
Package Type
TSSOP
Input Signal Type
Single-Ended
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-AD7927CBZ - BOARD EVALUATION FOR AD7927
Lead Free Status / Rohs Status
Compliant

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AD7927
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition. Figure 9 shows a typical INL
plot for the AD7927.
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Figure 10 shows a typical DNL plot for the AD7927.
Offset Error
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, that is, AGND + 1 LSB.
Offset Error Match
This is the difference in offset error between any two channels.
Gain Error
This is the deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (that is, REF
offset error has been adjusted out.
Gain Error Match
This is the difference in gain error between any two channels.
Zero Code Error
This applies when using the twos complement output coding
option, in particular to the 2 × REF
to +REF
the midscale transition (all 0s to all 1s) from the ideal V
voltage, that is, REF
Zero Code Error Match
This is the difference in zero code error between any two
channels.
Positive Gain Error
This applies when using the twos complement output coding
option, in particular to the 2 × REF
to +REF
last code transition (011. . .110) to (011 . . . 111) from the ideal
(that is, +REF
adjusted out.
Positive Gain Error Match
This is the difference in positive gain error between any two
channels.
IN
IN
biased about the REF
biased about the REF
IN
− 1 LSB) after the zero code error has been
IN
− 1 LSB.
IN
IN
point. It is the deviation of
point. It is the deviation of the
IN
IN
input range with −REF
input range with −REF
IN
− 1 LSB) after the
IN
IN
IN
Rev. A | Page 8 of 28
Negative Gain Error
This applies when using the twos complement output coding
option, in particular to the 2 × REF
to +REF
the first code transition (100 . . . 000) to (100 . . . 001) from the
ideal (that is, −REF
adjusted out.
Negative Gain Error Match
This is the difference in negative gain error between any two
channels.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale 400 kHz sine wave signal to all seven nonselected input
channels and determining how much that signal is attenuated
in the selected channel with a 50 kHz signal. The figure given is
the worst case across all eight channels for the AD7927.
Power Supply Rejection (PSR)
Variations in power supply affect the full-scale transition,
but not the converter’s linearity. Power supply rejection is the
maximum change in full-scale transition point due to a change
in power supply voltage from the nominal value (see the Typical
Performance Characteristics section).
Power Supply Rejection Ration (PSRR)
The power supply rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency (f) to the
power of a 200 mV p-p sine wave applied to the ADC AV
supply of frequency (f
where:
Pf is equal to the power at Frequency f in ADC output.
Pf
ADC AV
Here a 200 mV p-p sine wave is coupled onto the AV
Figure 6 shows the power supply rejection ratio vs. supply ripple
frequency for the AD7927 with no decoupling.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns into track mode at the
end of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1 LSB, after the end of conversion.
S
is equal to the power at Frequency f
PSRR(dB) = 10log(Pf/Pf
IN
DD
biased about the REF
.
IN
+ 1 LSB) after the zero code error has been
S
):
S
)
IN
point. It is the deviation of
IN
input range with −REF
S
coupled onto the
DD
supply.
DD
IN

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