AD7715ARZ-5 Analog Devices Inc, AD7715ARZ-5 Datasheet - Page 7

• Manufacturer Part Number: AD7715ARZ-5
• Description: IC ADC 16BIT SIGMA-DELTA 16-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7715ARZ-5

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 16
• Sampling Rate (per Second): 500
• Number Of Converters: 1
• Power Dissipation (max): 9.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.50mm Width)
• Resolution (bits): 16bit
• Sampling Rate: 500SPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Current: 1.1mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7715-3EBZ - BOARD EVALUATION FOR AD7715
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AV
2.4576 MHz, unless otherwise noted. All specifications T
Table 3.
Parameter
SYSTEM CALIBRATION
POWER REQUIREMENTS
1
2
3
4
5
6
7
After calibration, if the analog input exceeds positive full scale, the converter outputs all 1s. If the analog input is less than negative full scale, then the device outputs
all 0s.
These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV
The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
Assumes CLK Bit of setup register is set to correct status corresponding to the master clock frequency.
When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DV
crystal or resonator type (see the Clocking and Oscillator Circuit section).
Measured at dc and applies in the selected pass-band. PSRR at 50 Hz exceeds 120 dB with filter notches of 25 Hz or 50 Hz. PSRR at 60 Hz exceeds 120 dB with filter
notches of 20 Hz or 60 Hz.
PSRR depends on gain. Gain of 1:85 dB typical; gain of 2:90 dB typical; gains of 32 and 128:95 dB typical.
If the external master clock continues to run in standby mode, the standby current increases to 50 μA typical. When using a crystal or ceramic resonator across the
MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or resonator
type (see the Standby Mode section).
Positive Full-Scale Calibration Limit
Negative Full-Scale Calibration Limit
Offset Calibration Limit
Input Span
Power Supply Voltages
Power Supply Currents
Power Supply Rejection
Normal-Mode Power Dissipation
Normal-Mode Power Dissipation
Standby (Power-Down) Current
Standby (Power-Down) Current
DD
AV
AV
DV
AV
DV
= 3 V to 5 V, DV
DD
DD
DD
DD
DD
Voltage (AD7715-3)
Voltage (AD7715-5)
Current
Voltage
Current
2
4
DD
2
5
= 3 V to 5 V, REF IN(+) = 1.25 V (AD7715-3) or 2.5 V (AD7715-5); REF IN(−) = AGND; MCLK IN = 1 MHz to
7
7
4
4
1
1
Min
0.8 ×
V
3
4.75
3
REF
/GAIN
Typ
Depends on gain
MIN
to T
Rev. D | Page 7 of 40
Max
(1.05 ×
V
−(1.05 ×
V
−(1.05 ×
V
(2.1 × V
3.6
5.25
5.25
0.27
0.6
0.5
1.1
0.18
0.4
0.5
0.8
1.5
2.65
3.3
5.3
3.25
5
6.5
9.5
20
10
REF
REF
REF
6
MAX
)/GAIN
)/GAIN
)/GAIN
, unless otherwise noted.
REF
)/GAIN
Unit
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
dB
mW
mW
mW
mW
mW
mW
mW
mW
μA
μA
V
DD
current and power dissipation will vary depending on the
Conditions/Comments
GAIN Is the selected PGA gain (1, 2, 32, or 128)
GAIN Is the selected PGA gain (1, 2, 32, or 128)
GAIN Is the selected PGA gain (1, 2, 32, or 128)
GAIN Is the selected PGA gain (1, 2, 32, or 128)
GAIN Is the selected PGA gain (1, 2, 32, or 128)
For specified performance
For specified performance
For specified performance
AV
gain = 1 or 2 (f
Typically 0.2 mA; BUF bit of the setup register = 0
Typically 0.4 mA; BUF bit of the setup register = 1, AV
= 3.3 V or 5 V; gain = 32 or 128 (f
Typically 0.3 mA; BUF bit of the setup register = 0
Typically 0.8 mA; BUF bit of the setup register = 1
Digital inputs = 0 V or DV
Typically 0.15 mA. DV
Typically 0.3 mA. DV
Typically 0.4 mA. DV
Typically 0.6 mA. DV
AV
MCLK IN
BUF bit = 0. all gains 1 MHz clock
BUF bit = 1. all gains 1 MHz clock
BUF bit = 0. Gain = 32 or 128 @ f
BUF bit = 1. Gain = 32 or 128 @ f
AV
MCLK IN
BUF bit = 0; all gains 1 MHz clock
BUF bit = 1; all gains 1 MHz clock
BUF bit = 0; gain = 32 or 128 @ f
BUF bit = 1; gain = 32 or 128 @ f
External MCLK IN = 0 V or DV
External MCLK IN = 0 V or DV
DD
DD
DD
DD
= DV
= 3.3 V or 5 V. gain = 1 to 128 (f
= DV
+ 30 mV or go more negative than AGND − 30 mV.
DD
DD
= 3.3 V; digital inputs = 0 V or DV
= 5 V. digital inputs = 0 V or DV
CLK IN
= 2.4576 MHz)
DD
DD
DD
DD
= 5 V. f
= 3.3 V. f
= 5 V. f
= 3.3 V. f
DD
; external MCLK IN
DD
DD
. typically 10 μA; V
. typically 5 μA; V
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
= 1 MHz
= 2.4576 MHz
= 2.4576 MHz
CLK IN
= 2.4576 MHz
= 2.4576 MHz
= 2.4576 MHz
= 2.4576 MHz
= 2.4576 MHz)
= 1 MHz
= 1 MHz) or
AD7715
DD
DD
DD
; external
; external
DD
= 3.3 V
= 5 V
3
DD