AD7719BR-REEL Analog Devices Inc, AD7719BR-REEL Datasheet - Page 20

• Manufacturer Part Number: AD7719BR-REEL
• Description: IC ADC 16BIT 24BIT DUAL 28-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7719BR-REEL

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16/24
• Sampling Rate (per Second): 105
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 4.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• For Use With: EVAL-AD7719EB - BOARD EVAL FOR AD7719

AD7719
Status Register (A3, A2, A1, A0 = 0, 0, 0, 0; Power-On
Reset = 0x00)
The ADC Status register is an 8-bit read-only register. To access
the ADC Status register, the user must write to the Communica-
tions register selecting the next operation to be a read and loading
Bit
Location
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
R
D
S
Y
R
0
7
Bit
Name
RDY0
RDY1
CAL
NOXREF
ERR0
ERR1
0
LOCK
(
) 0
R
D
S
Y
R
Description
Ready Bit for Main ADC.
Set when data is written to main ADC data registers or on completion of calibration cycle. The RDY0 bit is
cleared automatically after the main ADC data register has been read or after a period of time before the
data register is updated with a new conversion result. This bit is also cleared by a write to the mode bits to
indicate a conversion or calibration.
Ready Bit for Aux ADC.
Set when data is written to aux ADC data registers or on completion of calibration cycle. The RDY1 bit is
cleared automatically after the aux ADC data register has been read or a period of time before the data register
is updated with a new conversion result. This bit is also cleared by a write to the mode bits to indicate a
conversion or calibration.
Calibration Status Bit.
Set to indicate completion of calibration. It is set at the same time that the RDY0 and/or RDY1 bits
are set high. Cleared by a write to the mode bits to start another ADC conversion or calibration.
No External Reference Bit. (Only active if main ADC is active and applies to REFIN1 only.)
Set to indicate that one or both of the REFIN1 pins is floating or the applied voltage is below a specified
threshold. When Set, conversion results are clamped to all 1s.
Cleared to indicate valid reference applied between REFIN1(+) and REFIN1(–).
Main ADC Error Bit.
Set to indicate that the result written to the main ADC data registers has been clamped to all 0s or all 1s.
After a calibration, this bit also flags error conditions that caused the calibration registers not to be written.
Error sources include Overrange, Underrange, and NOXREF.
Cleared by a write to the mode bits to initiate a conversion or calibration.
Aux ADC Error Bit.
Set to indicate that the result written to the Aux ADC data registers has been clamped to all 0s or all 1s.
After a calibration, this bit also flags error conditions that caused the calibration registers not to be written.
Error sources include Overrange, Underrange, and NOXREF.
Cleared by a write to the mode bits to initiate a conversion or calibration.
Reserved for Future Use.
PLL Lock Status Bit.
Set if the PLL has locked onto the 32 kHz crystal oscillator clock. If the user is worried about exact sampling
frequencies, for example, the LOCK bit should be interrogated and the result discarded if the LOCK bit is 0.
1
6
(
) 0
C
A
S
L
R
5
(
) 0
Table XI. Status Register Bit Designations
N
O
X
S
R
R
E
4
F
(
) 0
–20–
bits A3 to A0 with 0, 0, 0, 0. Table XI outlines the bit designations
for the Status register. SR0 through SR7 indicate the bit location,
with SR denoting that the bits are in the Status register. SR7
denotes the first bit of the data stream. The number in paren-
theses indicates the power-on/reset default status of that bit.
E
R
S
R
R
0
3
(
) 0
E
R
S
R
R
1
2
(
) 0
S
(
R
) 0
1
L
O
S
C
R
K
0
(
) 0
REV. A