AD7896AR Analog Devices Inc, AD7896AR Datasheet - Page 7

• Manufacturer Part Number: AD7896AR
• Description: IC ADC 12BIT SRL T/H HS 8-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7896AR

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Sampling Rate (per Second): 100k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 10.8mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Number Of Elements: 1
• Resolution: 12Bit
• Architecture: SAR
• Sample Rate: 100KSPS
• Input Polarity: Unipolar
• Input Type: Voltage
• Rated Input Volt: 5.5V
• Differential Input: No
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 10.8mW
• Differential Linearity Error: ±1LSB
• Integral Nonlinearity Error: ±1LSB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC N
• Input Signal Type: Single-Ended
• For Use With: EVAL-AD7896CBZ - BOARD EVALUATION FOR AD7896CBZ
• Lead Free Status / Rohs Status: Not Compliant

CONVERTER DETAILS
The AD7896 is a fast, 12-bit ADC that operates from a single
2.7 V to 5.5 V supply. It provides the user with a track-and-
hold, ADC, and serial interface logic functions on a single
chip. The ADC section of the AD7896 consists of a conven-
tional successive approximation converter based on an R-2R
ladder structure. The internal reference for the AD7896 is
derived from V
input range of 0 V to V
modes: the high sampling mode and the auto sleep mode
where the part automatically goes into sleep after the end of
conversion. These modes are discussed in more detail in the
Timing and Control section.
A major advantage of the AD7896 is that it provides all of the
preceding functions in an 8-lead package, PDIP or SOIC. This
offers the user considerable space saving advantages over alterna-
tive solutions. The AD7896 consumes only 9 mW typical, making
it ideal for battery-powered applications.
Conversion is initiated on the AD7896 by pulsing the CONVST
input. On the falling edge of CONVST, the on-chip track-and-
hold goes from track to hold mode and the conversion sequence
is started. The conversion clock for the part is generated inter-
nally using a laser-trimmed clock oscillator circuit. Conversion
time for the AD7896 is 8 µs in the high sampling mode (14 µs
for the auto sleep mode), and the track-and-hold acquisition
time is 1.5 µs. To obtain optimum performance from the part,
the read operation should not occur during the conversion or
during 400 ns prior to the next conversion. This allows the part
to operate at throughput rates up to 100 kHz and achieves data
sheet specifications (see the Timing and Control section).
CIRCUIT DESCRIPTION
Analog Input Section
The analog input range for the AD7896 is 0 V to V
V
This allows for a maximum output impedance of the circuit
driving the analog input of 1 kΩ. This ensures that the part will
be settled to 12-bit accuracy in the 1.5 µs acquisition time. This
input is benign with dynamic charging currents. The designed
code transitions occur on successive integer LSB values (i.e.,
1 LSB, 2 LSB, 3 LSB, . . . , FS – 1 LSB). Output coding is straight
(natural) binary with 1 LSB = FS/4096 = 3.3 V/4096 = 0.81 mV.
The ideal input/output transfer function is shown in Table I.
Analog Input
+FSR – 1 LSB
+FSR – 2 LSB (3.298389)
+FSR/2 – 3 LSB (3.297583)
AGND + 3 LSB (0.002417)
AGND + 2 LSB (0.001611)
AGND + 1 LSB (0.000806)
NOTES
1
2
Track-and-Hold Section
The track-and-hold amplifier on the analog input of the AD7896
allows the ADC to accurately convert an input sine wave of full-
scale amplitude to 12-bit accuracy. The input bandwidth of the
REV. C
FSR is full-scale range and is 3.3 V with V
1 LSB = FSR/4096 = 0.81 mV with V
IN
Table I. Ideal Input/Output Code Table for the AD7896
pin drives the input to the track-and-hold amplifier directly.
1
2
DD
(3.299194)
, which allows the part to accept an analog
DD
. The AD7896 has two operating
DD
= +3.3 V.
DD
Code Transition
111 . . . 110 to 111 . . . 111
111 . . . 101 to 111 . . . 110
111 . . . 100 to 111 . . . 101
000 . . . 010 to 000 . . . 011
000 . . . 001 to 000 . . . 010
000 . . . 000 to 000 . . . 001
= +3.3 V.
DD.
The
–7–
track-and-hold is greater than the Nyquist rate of the ADC even
when the ADC is operated at its maximum throughput rate of
100 kHz (i.e., the track-and-hold can handle input frequencies
in excess of 50 kHz).
The track-and-hold amplifier acquires an input signal to 12-bit
accuracy in less than 1.5 µs. The operation of the track-and-
hold is essentially transparent to the user. With the high sampling
operating mode, the track-and-hold amplifier goes from its
tracking mode to its hold mode at the start of conversion (i.e.,
the rising edge of CONVST). The aperture time for the track-
and-hold (i.e., the delay time between the external CONVST
signal and the track-and-hold actually going into hold) is typi-
cally 15 ns. At the end of conversion (on the falling edge of
BUSY), the part returns to its tracking mode. The acquisition
time of the track-and-hold amplifier begins at this point. For the
auto shutdown mode, the rising edge of CONVST wakes up the
part and the track-and-hold amplifier goes from its tracking
mode to its hold mode 6 µs after the rising edge of CONVST
(provided that the CONVST high time is less than 6 µs). Once
again the part returns to its tracking mode at the end of conver-
sion when the BUSY signal goes low.
Timing and Control
Figure 2 shows the timing and control sequence required to
obtain optimum performance from the AD7896. In the
sequence shown, conversion is initiated on the falling edge of
CONVST and new data from this conversion is available in the
output register of the AD7896 8 µs later. Once the read opera-
tion has taken place, another 400 ns should be allowed before
the next falling edge of CONVST to optimize the settling of the
track-and-hold amplifier before the next conversion is initiated.
With the serial clock frequency at its maximum of 10 MHz (5 V
operation), the achievable throughput time for the part is 8 µs
(conversion time) plus 1.6 µs (read time) plus 0.4 µs (acquisi-
tion time). This results in a minimum throughput time of 10 µs
(equivalent to a throughput rate of 100 kHz). A serial clock of
less than 10 MHz can be used, but this will in turn mean that
the throughput time will increase.
The read operation consists of 16 serial clock pulses to the output
shift register of the AD7896. After 16 serial clock pulses, the shift
register is reset and the SDATA line is three-stated. If there are
more serial clock pulses after the 16th clock, the shift register will
be moved on past its reset state. However, the shift register will be
reset again on the falling edge of the CONVST signal to ensure
that the part returns to a known state every conversion cycle. As a
result, a read operation from the output register should not
straddle across the falling edge of CONVST as the output shift
register will be reset in the middle of the read operation and the
data read back into the microprocessor will appear invalid.
The throughput rate of the part can be increased by reading
data during conversion. If the data is read during conversion, a
throughput time of 8 µs (conversion time) plus 1.5 µs (acquisi-
tion time) is achieved when a 10 MHz, (5 V operation) serial
clock is being used. This minimum throughput time of 9.5 µs is
achieved with a slight reduction in performance from the AD7896.
The advantage of this arrangement is that when the serial clock
is significantly lower than 10 MHz, the throughput time for this
arrangement will be significantly less than the throughput time
where the data is read after conversion. The signal-to-(noise +
distortion) number is likely to degrade by less than 1 dB while
the code flicker from the part will also increase (see the AD7896
Performance section).
AD7896