AD7714YRUZ Analog Devices Inc, AD7714YRUZ Datasheet - Page 17

• Manufacturer Part Number: AD7714YRUZ
• Description: IC ADC SIGNAL COND 3/5V 24-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7714YRUZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 24
• Sampling Rate (per Second): 1k
• Number Of Converters: 1
• Power Dissipation (max): 7mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 24bit
• Sampling Rate: 1kSPS
• Input Channel Type: Differential
• Supply Voltage Range - Digital: 2.7V To 5.25V
• Supply Current: 1.1mA
• Number Of Elements: 1
• Resolution: 24Bit
• Architecture: Delta-Sigma
• Sample Rate: 1KSPS
• Input Polarity: Unipolar/Bipolar
• Input Type: Voltage
• Differential Input: Yes
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 3/5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 4.75mW
• Integral Nonlinearity Error: ±0.0015%FSR
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7714-3EBZ - BOARD EVALUATION FOR AD7714
• Lead Free Status / Rohs Status: Compliant

REV. C
Filter Registers. Power On/Reset Status: Filter High Register: 01 Hex. Filter Low Register: 40 Hex.
There are two 8-bit Filter Registers on the AD7714 from which data can either be read or to which data can be written. Tables IX
and X outline the bit designations for the Filter Registers.
B/U
WL
BST
ZERO
CLKDIS
FS11–FS0
B/U
B/U
FS7
Bipolar/Unipolar Operation. A 0 in this bit selects Bipolar Operation. This is the default (Power-On or RESET)
status of this bit. A 1 in this bit selects unipolar operation.
Word Length. A 0 in this bit selects 16-bit word length when reading from the data register (i.e., DRDY returns
high after 16 serial clock cycles in the read operation). This is the default (Power-On or RESET) status of this
bit. A 1 in this bit selects 24-bit word length.
Current Boost. A 0 in this bit reduces the current taken by the analog front end. When the part is operated with
f
drawn from AV
ated at gains of 8 to 128 with f
device. The Power-On or RESET status of this bit is 0.
To ensure correct operation of the A Versions of the part, a 0 must be written to this bit.
Master Clock Disable Bit. A Logic 1 in this bit disables the master clock from appearing at the MCLKOUT
pin. When disabled, the MCLKOUT pin is forced low. This feature allows the user the flexibility of using the
MCLKOUT as a clock source for other devices in the system or for turning off the MCLKOUT as a power
saving feature. When using an external master clock or the MCLKIN pin, the AD7714 continues to have inter-
nal clocks and will convert normally with its CLKDIS bit active. When using a crystal oscillator or ceramic
resonator across the MCLK IN or MCLKOUT pins, the AD7714 clock is stopped and no conversions take
place when the CLKDIS bit is active.
Filter Selection. The on-chip digital filter provides a Sinc
programmed into these bits determine the filter cut-off frequency, the position of the first notch of the filter and
the data rate for the part. In association with the gain selection, it also determines the output noise (and hence
the effective resolution) of the device.
The first notch of the filter occurs at a frequency determined by the relationship:
where code is the decimal equivalent of the code in bits FS0 to FS11 and is in the range 19 to 4,000. With the
nominal f
ensure correct operation of the AD7714, the value of the code loaded to these bits must be within this range.
Failure to do this will result in unspecified operation of the device.
Changing the filter notch frequency, as well as the selected gain, impacts resolution. Tables I through IV show
the effect of the filter notch frequency and gain on the effective resolution of the AD7714. The output data rate
(or effective conversion time) for the device is equal to the frequency selected for the first notch of the filter. For
example, if the first notch of the filter is selected at 50 Hz then a new word is available at a 50 Hz rate or every
20 ms. If the first notch is at 1 kHz, a new word is available every 1 ms.
The settling time of the filter to a full-scale step input change is worst case 4 1/(output data rate). For
example, with the first filter notch at 50 Hz, the settling time of the filter to a full-scale step input change is
80 ms max. This settling time can be reduced to 3
change to a reset of the digital filter. In other words, if the step input takes place with the SYNC input low or
the FSYNC bit high, the settling time will be 3
FSYNC returns low. If a change of channel takes place, the settling time is 3 1/(output data rate) regardless of
the SYNC or FSYNC status as the part issues an internal SYNC command when requested to change channels.
The –3 dB frequency is determined by the programmed first notch frequency according to the relationship:
CLK IN
FS6
WL
WL
= 1 MHz or at gains of 1 to 4 with f
CLK IN
DD
of 2.4576 MHz, this results in a first notch frequency range from 4.8 Hz to 1.01 kHz. To
FS5
, although the device will operate just as well with this bit at a 1. When the AD7714 is oper-
BST
BST
Table IX. Filter High Register (RS2–RS0 = 0, 1, 0)
Table X. Filter Low Register (RS2–RS0 = 0, 1, 1)
filter –3 dB frequency = 0.262 filter first notch frequency.
ZERO
CLKDIS
FS4
CLK IN
filter first notch frequency = (f
= 2.4576 MHz, this bit must be 1 to ensure correct operation of the
–17–
FS3
FS11
FS11
CLK IN
= 2.4576 MHz, this bit should be 0 to reduce the current
1/(output data rate) from when SYNC returns high or
FS2
1/(output data rate) by synchronizing the step input
FS10
FS10
3
(or (Sinx/x)
CLK IN
FS1
FS9
FS9
/128)/code
3
) filter response. The 12 bits of data
FS0
FS8
FS8
A Versions
Y Versions
All Versions
AD7714
2