CS5506-BSZ Cirrus Logic Inc, CS5506-BSZ Datasheet
CS5506-BSZ
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CS5506-BSZ Summary of contents
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... The CS 5507/8 have single-channel differential analog and reference inputs while the CS5505/6 have four pseudo-differential analog input channels. The CS5505/7 have a 16-bit output word. The CS5506/8 have a 20-bit output word.The CS5505/6/7/8 sample upon command up to 100 Sps. The on-chip digital filter offers superior line rejection at 50 and 60 Hz when the device is operated from a 32 ...
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ANALOG CHARACTERISTICS 3.3V ± 5%; VREF+ = 2.5V(external); VREF AGND at AIN; Anal og input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2) Parameter* Specified Temperature Range Accuracy Linearity Error Differential Nonlinearity Full ...
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... FS ppm FS 0.0000238 0.24 0.0000477 0.47 0.0000954 0.95 0.0001907 1.91 0.0003814 3.81 VREF = 2.5V CS5506/8; 20-Bit Unit Conversion Factors Symbol out f -3dB t s CS5505/6/7/8 CS5505/6/7 Ω with a source CS5508-S Max Min Typ Max -55 to +125 - 0.0015 0.003 ...
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... XIN = 32.768 kHz. Guaranteed by design and / or characterization. 7. All outputs unloaded inputs CMOS levels. SLEEP mode controlled by M/SLP pin. SLEEP active = M/SLP pin at (VD+)/2 input level VA ± 10%; VA ± 10%; VD MIN MAX = 32.768kHz ; Bipolar Mode; R CLK CS5505/7 CS5506/8 Min Typ Max - +2.5 (Note 5) ±2 105 - 120 - - ...
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DIGITAL CHARACTERISTICS DGND = 0.) All measurements below are performed under static conditions. (Note 2) Parameter High-Level Input Voltage: All Pins Except XIN and M/SLP Low-Level Input Voltage: All Pins Except XIN and M/SLP M/SLP SLEEP Active Threshold High-Level ...
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SWITCHING CHARACTERISTICS VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C Parameter Master Clock Frequency: Internal Oscillator: External Clock: Master Clock Duty Cycle Rise Times: Any Digital Input Any Digital Output Fall ...
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SWITCHING CHARACTERISTICS VD+ = 3.3V ± 5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic pF.) (Note 2) Parameter Master Clock Frequency: Internal Oscillator: External Clock: Master Clock ...
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XIN XIN/2 CAL CONV STATE Standby XIN XIN/2 A0 CONV DRDY BP/UP STATE Standby ccw t t scl cal Calibration Figure 1. Calibration Timing (Not to Scale) t hca sac t cpw t t scn ...
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SWITCHING CHARACTERISTICS VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C Parameter SSC Mode (M/SLP = VD+) Access Time: CS Low to SDATA out (DRDY = low) DRDY falling to MSB (CS ...
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SWITCHING CHARACTERISTICS 5%; VA ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C Parameter SSC Mode (M/SLP = VD+) Access Time: CS Low to SDATA out (DRDY = low) DRDY falling to ...
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XIN XIN/2 CONV CS STATE Standby Conversion DRDY SCLK(o) Hi-Z SDATA(o) Hi-Z STATE (CONV held high) Conversion1 Figure 3. Timing Relationships; SSC Mode (Not to Scale) DRDY CS t csd2 SDATA(o) Hi-Z SCLK(i) DRDY CS t csd2 SDATA(o) Hi-Z SCLK(i) ...
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RECOMMENDED OPERATING CONDITIONS Parameter DC Power Supplies: Positive Digital (VA+)-(VA-) Positive Analog Negative Analog Analog Reference Voltage (Note 20) (VREF+)-(VREF-) Analog Input Voltage: (Note 21) Unipolar Bipolar Notes: 19. All voltages with r espect to ground. 20. The CS5505/6/7/8 can ...
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... The CS5505/6/7/8 are very low power mono- lith A/D co nverters designed specifically for measurement of dc signals. The CS5505/7 are 16-bit converters (a four channel and a single channel version). The CS5506/8 are 20-bit converters (a four channel and a single channel version). Each of the devices includes a delta-sigma charge-balance converter, a voltage reference, a calibration microcontroller with SRAM, a digital filter and a serial interface ...
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... Note that any time CONV transitions from low to high, the multiplexer inputs A0 and A1 are latched internal to the CS5505 and CS5506 de- vices. These latched inputs select the analog input channel which will be used once conver- sion commences ...
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... BP/UP pin controls how the output word from the digital filter is processed. In bipolar mode the output word computed by the digital filter is offset by 8000H in the 16-bit CS5505/7 or 80000H in 20-bit CS5506/8 (see Understanding Converter Calibration). BP/UP can be changed after a conversion is started as long stable for 82 clock cycles of the conversion period prior to DRDY falling ...
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... The CS5505/6/7/8 converters output data in bi- nary format when converting unipolar signals and in offset binary format when converting bi- polar signals. Table 2 outlines the output coding for the 16-bit CS5505/7 and the 20-bit CS5506/8 in both unipolar and bipolar measurement modes. Bipolar Input ...
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... The CS5505/6/7/8 A/D converters have excellent linearity performance. Calibration minimizes the errors in offset and gain. The CS5505/7 devices have no missing code performance to 16-bits. The CS5506/8 devices have no missing code performance to 20-bits. Figure 7 illustrates the DNL of the 16-bit CS5505. The converters achieve Common Mode Rejection (CMR 105 dB typical, and CMR at 50 and 120 dB typical ...
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... CS5505 (1/4LSB at 16-bits) and 600 nV in the CS5506 (1/4LSB at 20-bits), the above equa- tion indicates that when operating from a 32.768 kHz XIN, source resistances up to 110 kΩ in the CS5505 or 84 kΩ in the CS5506 15 pF are acceptable in the absence of external capaci- Internal tance (C EXT = 0) ...
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Digital Filter Characteristics The digital filter in the CS5505/6/7/8 is the com- bination of a comb filter and a low pass filter. The comb filter has zeros in its transfer function which are optimally placed to reject line interfer- ence ...
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If the CS5505/6/7/8 is operated at a clock rate other than 32.768 kHz, the filter characteristics, including the comb filter zeros, will scale with the operating clock frequency. Therefore, opti- mum rejection of line frequency interference will occur with the ...
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Over the military temperature range (- 55 to +125 °C) the on-chip gate oscillator is designed to work only with a 32.768 kHz crys- tal. The chip will ...
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Synchronous External-Clocking Mode The serial port operates in the SEC mode when the M/SLP pin is connected to the DGND pin. SDATA is the output pin for the serial data. When CS goes low after new data becomes available (DRDY ...
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No analog ground pin is re- quired because the inputs for measurement and for the voltage reference are differential and re- quire no ground. In the digital section of the chip the supply current flows into the ...
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Figure 14 illustrates the System Connection Dia- gram for the CS5505/6 using a single +5V supply. Note that all supply pins are bypassed with 0.1 µF capacitors and that the VD+ digital supply is derived from the VA+ supply. Figure ...
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Analog Supply Calibration Control Bipolar/ Unipolar Input Select Analog* Signal Sources Signal Ground *Unused analog inputs should be tied to AIN- + Voltage (1) Reference - Note: (1) To use the internal 2.5 volt reference see Figure 6. (2) ...
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PIN CONNECTIONS* MULTIPLEXER SELECTION INPUT CHIP SELECT CONVERT CALIBRATE CRYSTAL IN CRYSTAL OUT SE RIAL MODE/ SLEEP BIPOLAR/UNIPOLAR DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG RETURN DIFFERENTIAL ANALOG INPUT CHIP SELECT CONVERT CALIBRATE CRYSTAL IN CRYSTAL OUT SERIAL MODE/ ...
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PIN DESCRIPTIONS Pin numbers for four channel devices are in parentheses. Clock Generator XIN; XOUT - Crystal In; Crystal Out, Pins 4 (5) and 5 (6). A gate inside the chip is connected to these pins and can be used ...
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Control Input Pins CAL - Calibrate, Pin 3 (4). When taken high the same time that the CONV pin is taken high the converter will perform a self-calibration which includes calibration of the offset and gain scale factors in the ...
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VD+ - Positive Digital Power, Pin 17 (20). Positive digital supply voltage. Nominally +5 volts or 3.3 volts. DGND - Digital Ground, Pin 16 (19). Digital Ground. Other Connection, Pin 9. Pin should be left floating. SPECIFICATION ...
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... CS5505-ASZ (lead free) CS5506-BSZ (lead free) CS5507-ASZ (lead free) CS5508-BSZ (lead free) ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5505-ASZ (lead free) CS5506-BSZ (lead free) CS5507-ASZ (lead free) CS5508-BSZ (lead free) * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 30 Liearity Error Channels 16 Bits 0 ...
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REVISION HISTORY Revision Date F4 MAR 1995 First Final Release F5 AUG 2005 Updated device ordering info. Updated legal notice. Added MSL data.. F7 OCT 2009 Increased minimum Vdiff voltage from 4.5 to 4.75 V. Contacting Cirrus Logic Support For ...
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NOTES - CS5505/6/7/8 DS59F7 ...
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Evaluation Board for CS5505/6/7/8 Series of ADC’s Evaluation Board for CS5505/6/7/8 Series of ADCs Features l Operation with on-board 32.768 kHz crystal or off-board clock source l Jumper selectable: - SSC mode; SEC mode; Sleep l DIP Switch Selectable: - ...
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Introduction The CDB5505/6/7/8 evaluation board provides a quick means of testing the CS5505/6/7/8 series A/D converters. The CS5505/6/7/8 converters require a minimal amount of external circuitry. The evaluation board comes configured with the A/D converter chip operating from a 32.768 ...
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DS59DB4 DS59DB2 CDB5505/6/7/8 CS5505/6/7 ...
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A0 and A1 (see Table 1). Once A0 and A1 are selected, the CONV switch (S2-3) must be switched on (closed) and then open to cause the CONV signal to transition low to high. This latches the A0 and ...
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Figure 3. Top Ground Plane Layer (NOT TO SCALE) DS59DB4 DS59DB2 CDB5505/6/7/8 CS5505/6/7 ...
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Figure 4. Bottom Trace Layer (NOT TO SCALE CDB5505/6/7/8 CS5505/6/7/8 DS59DB4 DS59DB2 ...
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DS59DB4 DS59DB2 Figure 5. Silk Screen Layer (NOT TO SCALE) CDB5505/6/7/8 CS5505/6/7 ...
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REVISION HISTORY Revision Date DB2 MAR 1995 First Release F5 AUG 2005 Updated legal notice. DB4 JUN 2009 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to ...